Searched refs:val (Results 351 - 375 of 11012) sorted by relevance

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/linux-master/drivers/media/pci/ddbridge/
H A Dddbridge-i2c.h44 static int __maybe_unused i2c_read(struct i2c_adapter *adapter, u8 adr, u8 *val) argument
47 .buf = val, .len = 1 } };
53 u8 adr, u8 reg, u8 *val, u8 len)
58 .buf = val, .len = len } };
64 u8 adr, u16 reg, u8 *val, u8 len)
70 .buf = val, .len = len } };
76 u8 adr, u16 reg, u8 val)
78 u8 msg[3] = { reg >> 8, reg & 0xff, val };
84 u8 adr, u8 reg, u8 val)
86 u8 msg[2] = { reg, val };
52 i2c_read_regs(struct i2c_adapter *adapter, u8 adr, u8 reg, u8 *val, u8 len) argument
63 i2c_read_regs16(struct i2c_adapter *adapter, u8 adr, u16 reg, u8 *val, u8 len) argument
75 i2c_write_reg16(struct i2c_adapter *adap, u8 adr, u16 reg, u8 val) argument
83 i2c_write_reg(struct i2c_adapter *adap, u8 adr, u8 reg, u8 val) argument
91 i2c_read_reg16(struct i2c_adapter *adapter, u8 adr, u16 reg, u8 *val) argument
97 i2c_read_reg(struct i2c_adapter *adapter, u8 adr, u8 reg, u8 *val) argument
[all...]
/linux-master/include/linux/mfd/
H A Dtmio.h19 #define tmio_iowrite8(val, addr) writeb((val), (addr))
20 #define tmio_iowrite16(val, addr) writew((val), (addr))
22 #define tmio_iowrite32(val, addr) \
24 writew((val), (addr)); \
25 writew((val) >> 16, (addr) + 2); \
28 #define sd_config_write8(base, shift, reg, val) \
29 tmio_iowrite8((val), (base) + ((reg) << (shift)))
30 #define sd_config_write16(base, shift, reg, val) \
[all...]
/linux-master/drivers/clocksource/
H A Dtimer-mediatek-cpux.c43 static void mtk_cpux_writel(u32 val, u32 reg_idx, struct timer_of *to) argument
46 writel(val, timer_of_base(to) + CPUX_CON_REG);
52 u32 val; local
54 val = mtk_cpux_readl(CPUX_IDX_GLOBAL_IRQ, to);
57 val |= *irq_mask;
59 val &= ~(*irq_mask);
61 mtk_cpux_writel(val, CPUX_IDX_GLOBAL_IRQ, to);
102 u32 freq, val; local
126 val = mtk_cpux_readl(CPUX_IDX_GLOBAL_CTRL, &to);
127 val
[all...]
/linux-master/drivers/net/ethernet/ti/icssg/
H A Dicssg_mii_cfg.c17 u32 val; local
22 regmap_read(mii_rt, PRUSS_MII_RT_TX_IPG0, &val);
24 regmap_write(mii_rt, PRUSS_MII_RT_TX_IPG0, val);
72 u32 val, mask, shift; local
77 val = MII_MODE_RGMII;
79 val = MII_MODE_MII;
81 val <<= shift;
82 regmap_update_bits(miig_rt, ICSSG_CFG_OFFSET, mask, val);
83 regmap_read(miig_rt, ICSSG_CFG_OFFSET, &val);
88 u32 val; local
[all...]
/linux-master/arch/mips/pci/
H A Dops-rc32434.c73 int where, u8 *val)
79 *val = (data >> ((where & 3) << 3)) & 0xff;
84 int where, u16 *val)
90 *val = (data >> ((where & 3) << 3)) & 0xffff;
95 int where, u32 *val)
108 ret = config_access(PCI_ACCESS_READ, bus, devfn, where, val);
130 u8 val)
138 (val << ((where & 3) << 3));
149 u16 val)
157 (val << ((wher
72 read_config_byte(struct pci_bus *bus, unsigned int devfn, int where, u8 *val) argument
83 read_config_word(struct pci_bus *bus, unsigned int devfn, int where, u16 *val) argument
94 read_config_dword(struct pci_bus *bus, unsigned int devfn, int where, u32 *val) argument
129 write_config_byte(struct pci_bus *bus, unsigned int devfn, int where, u8 val) argument
148 write_config_word(struct pci_bus *bus, unsigned int devfn, int where, u16 val) argument
168 write_config_dword(struct pci_bus *bus, unsigned int devfn, int where, u32 val) argument
177 pci_config_read(struct pci_bus *bus, unsigned int devfn, int where, int size, u32 *val) argument
190 pci_config_write(struct pci_bus *bus, unsigned int devfn, int where, int size, u32 val) argument
[all...]
/linux-master/include/linux/mlx4/
H A Ddoorbell.h55 static inline void mlx4_write64(__be32 val[2], void __iomem *dest, argument
58 __raw_writeq(*(u64 *) val, dest);
73 static inline void mlx4_write64(__be32 val[2], void __iomem *dest, argument
79 __raw_writel((__force u32) val[0], dest);
80 __raw_writel((__force u32) val[1], dest + 4);
/linux-master/arch/sparc/kernel/
H A Djump_label.c16 u32 val; local
31 val = 0x10680000 | (((u32) off >> 2) & 0x7ffff);
37 val = 0x10800000 | (((u32) off >> 2) & 0x3fffff);
40 val = 0x01000000;
44 *insn = val;
/linux-master/drivers/media/usb/pvrusb2/
H A Dpvrusb2-ctrl.h20 int pvr2_ctrl_set_value(struct pvr2_ctrl *,int val);
23 int pvr2_ctrl_set_mask_value(struct pvr2_ctrl *,int mask,int val);
69 /* Convert a given mask/val to a custom symbolic value */
71 int mask,int val,
80 /* Convert a given mask/val to a symbolic value */
82 int mask,int val,
91 /* Convert a given mask/val to a symbolic value - must already be
94 int mask,int val,
/linux-master/drivers/net/ethernet/huawei/hinic/
H A Dhinic_hw_qp_ctxt.h20 #define HINIC_SQ_CTXT_CEQ_ATTR_SET(val, member) \
21 (((u32)(val) & HINIC_SQ_CTXT_CEQ_ATTR_##member##_MASK) \
30 #define HINIC_SQ_CTXT_CI_SET(val, member) \
31 (((u32)(val) & HINIC_SQ_CTXT_CI_##member##_MASK) \
40 #define HINIC_SQ_CTXT_WQ_PAGE_SET(val, member) \
41 (((u32)(val) & HINIC_SQ_CTXT_WQ_PAGE_##member##_MASK) \
58 #define HINIC_SQ_CTXT_PREF_SET(val, member) \
59 (((u32)(val) & HINIC_SQ_CTXT_PREF_##member##_MASK) \
66 #define HINIC_SQ_CTXT_WQ_BLOCK_SET(val, member) \
67 (((u32)(val)
[all...]
H A Dhinic_hw_cmdq.h30 #define HINIC_CMDQ_CTXT_PAGE_INFO_SET(val, member) \
31 (((u64)(val) & HINIC_CMDQ_CTXT_##member##_MASK) \
34 #define HINIC_CMDQ_CTXT_PAGE_INFO_GET(val, member) \
35 (((u64)(val) >> HINIC_CMDQ_CTXT_##member##_SHIFT) \
38 #define HINIC_CMDQ_CTXT_PAGE_INFO_CLEAR(val, member) \
39 ((val) & (~((u64)HINIC_CMDQ_CTXT_##member##_MASK \
48 #define HINIC_CMDQ_CTXT_BLOCK_INFO_SET(val, member) \
49 (((u64)(val) & HINIC_CMDQ_CTXT_##member##_MASK) \
52 #define HINIC_CMDQ_CTXT_BLOCK_INFO_GET(val, member) \
53 (((u64)(val) >> HINIC_CMDQ_CTXT
[all...]
/linux-master/net/ethtool/
H A Dbitset.h11 int ethnl_bitset_size(const unsigned long *val, const unsigned long *mask,
14 int ethnl_bitset32_size(const u32 *val, const u32 *mask, unsigned int nbits,
17 const unsigned long *val, const unsigned long *mask,
20 int ethnl_put_bitset32(struct sk_buff *skb, int attrtype, const u32 *val,
29 int ethnl_parse_bitset(unsigned long *val, unsigned long *mask,
/linux-master/tools/testing/selftests/bpf/progs/
H A Dtest_mmap.c31 __u64 val, *p; local
41 val = (*p) * 2;
42 bpf_map_update_elem(&data_map, &one, &val, 0);
46 val = in_val * 3;
47 bpf_map_update_elem(&data_map, &far, &val, 0);
/linux-master/tools/testing/selftests/powerpc/pmu/ebb/
H A Dno_handler_test.c19 u64 val; local
34 val = mfspr(SPRN_EBBHR);
35 FAIL_IF(val != 0);
48 val = mfspr(SPRN_MMCR0);
49 FAIL_IF(val != 0x0000000080000080);
/linux-master/arch/arm/mach-bcm/
H A Dbcm63xx_pmb.c61 unsigned int addr, u32 off, u32 *val,
66 ret = bpcm_wr(master, addr, off, *val);
71 ret = bpcm_rd(master, addr, off, val);
76 } while (((*val >> shift) & mask) != cond);
129 u32 val, ctrl; local
156 ret = bpcm_rd(base, addr, ARM_PWR_CONTROL(cpu), &val);
160 val |= (PWR_CPU_MASK << PWR_ON_SHIFT);
162 ret = bpcm_wr_rd_mask(base, addr, ARM_PWR_CONTROL(cpu), &val,
167 val |= (PWR_CPU_MASK << PWR_OK_SHIFT);
169 ret = bpcm_wr_rd_mask(base, addr, ARM_PWR_CONTROL(cpu), &val,
60 bpcm_wr_rd_mask(void __iomem *master, unsigned int addr, u32 off, u32 *val, u32 shift, u32 mask, u32 cond) argument
[all...]
H A Dboard_bcm281xx.c21 uint32_t val; local
38 val = readl(base + SECWDOG_OFFSET);
39 val &= SECWDOG_RESERVED_MASK | SECWDOG_WD_LOAD_FLAG_MASK;
40 val |= SECWDOG_EN_MASK | SECWDOG_SRSTEN_MASK |
43 writel(val, base + SECWDOG_OFFSET);
/linux-master/arch/powerpc/include/asm/book3s/32/
H A Dmmu-hash.h198 static __always_inline void update_user_segment(u32 n, u32 val)
201 mtsr(val + n * 0x111, n << 28);
204 static __always_inline void update_user_segments(u32 val)
206 val &= 0xf0ffffff;
208 update_user_segment(0, val);
209 update_user_segment(1, val);
210 update_user_segment(2, val);
211 update_user_segment(3, val);
212 update_user_segment(4, val);
213 update_user_segment(5, val);
[all...]
/linux-master/drivers/atm/
H A Dnicstarmac.c104 #define NICSTAR_REG_WRITE(bs, reg, val) \
106 writel((val),(base)+(reg))
119 u_int32_t val;
124 val = NICSTAR_REG_READ(base, NICSTAR_REG_GENERAL_PURPOSE) & 0xFFFFFFF0;
128 (val | rdsrtab[i]));
138 (val | clocktab[j++]));
142 (val | clocktab[j++]));
159 u_int32_t val = 0; local
163 val = NICSTAR_REG_READ(base, NICSTAR_REG_GENERAL_PURPOSE) & 0xFFFFFFF0;
168 (val | readta
204 u_int32_t val; local
[all...]
/linux-master/arch/loongarch/include/asm/
H A Dirqflags.h18 "csrxchg %[val], %[mask], %[reg]\n\t"
19 : [val] "+r" (flags)
28 "csrxchg %[val], %[mask], %[reg]\n\t"
29 : [val] "+r" (flags)
38 "csrxchg %[val], %[mask], %[reg]\n\t"
39 : [val] "+r" (flags)
48 "csrxchg %[val], %[mask], %[reg]\n\t"
49 : [val] "+r" (flags)
58 "csrrd %[val], %[reg]\n\t"
59 : [val] "
[all...]
/linux-master/drivers/block/drbd/
H A Ddrbd_state.h39 ({ union drbd_state val; val.i = 0; val.T = (S); val; })
43 ({ union drbd_state val; val.i = 0; val.T1 = (S1); \
44 val.T2 = (S2); val; })
48 ({ union drbd_state val; va
157 drbd_request_state(struct drbd_device *device, union drbd_state mask, union drbd_state val) argument
[all...]
/linux-master/tools/perf/util/
H A Dcs-etm-base.c62 static int cs_etm__print_cpu_metadata_v0(u64 *val, int *offset) argument
68 magic = val[i + CS_ETM_MAGIC];
77 fprintf(stdout, cs_etm_priv_fmts[CS_ETM_MAGIC], val[i++]);
78 fprintf(stdout, cs_etm_priv_fmts[CS_ETM_CPU], val[i++]);
85 fprintf(stdout, cs_etm_priv_fmts[j], val[i]);
91 fprintf(stdout, cs_etmv4_priv_fmts[j], val[i]);
97 static int cs_etm__print_cpu_metadata_v1(u64 *val, int *offset) argument
102 magic = val[i + CS_ETM_MAGIC];
104 total_params = val[i + CS_ETM_NR_TRC_PARAMS] + CS_ETM_COMMON_BLK_MAX_V1;
110 fprintf(stdout, param_unk_fmt, j, val[
139 cs_etm__print_auxtrace_info(u64 *val, int num) argument
[all...]
/linux-master/arch/x86/include/asm/
H A Dibt.h68 static inline bool is_endbr(u32 val) argument
70 if (val == gen_endbr_poison())
73 val &= ~0x01000000U; /* ENDBR32 -> ENDBR64 */
74 return val == gen_endbr();
101 static inline bool is_endbr(u32 val) { return false; } argument
/linux-master/drivers/clk/sunxi-ng/
H A Dccu_mmc_timing.c25 u32 val; local
32 val = readl(cm->base + cm->reg);
34 val |= CCU_MMC_NEW_TIMING_MODE;
36 val &= ~CCU_MMC_NEW_TIMING_MODE;
37 writel(val, cm->base + cm->reg);
/linux-master/drivers/ata/
H A Dahci_tegra.c185 u32 val; local
188 val = readl(tegra->sata_aux_regs + SATA_AUX_MISC_CNTL_1_0);
189 val &= ~SATA_AUX_MISC_CNTL_1_0_SDS_SUPPORT;
190 writel(val, tegra->sata_aux_regs + SATA_AUX_MISC_CNTL_1_0);
199 u32 val; local
202 ret = tegra_fuse_readl(FUSE_SATA_CALIB, &val);
206 calib = tegra124_pad_calibration[val & FUSE_SATA_CALIB_MASK];
210 val = readl(tegra->sata_regs +
212 val &= ~T_SATA0_CHX_PHY_CTRL1_GEN1_TX_AMP_MASK;
213 val
301 u32 val; local
[all...]
/linux-master/drivers/soc/qcom/
H A Dkryo-l2-accessors.c19 * @val: Value to be written to register.
24 void kryo_l2_set_indirect_reg(u64 reg, u64 val) argument
31 write_sysreg_s(val, L2CPUSRDR_EL1);
46 u64 val; local
52 val = read_sysreg_s(L2CPUSRDR_EL1);
55 return val;
/linux-master/drivers/media/pci/mgb4/
H A Dmgb4_regs.h18 #define mgb4_write_reg(regs, offset, val) \
19 iowrite32(val, (regs)->membase + (offset))
24 u32 val)
28 val |= ret & ~mask;
29 mgb4_write_reg(regs, reg, val);
23 mgb4_mask_reg(struct mgb4_regs *regs, u32 reg, u32 mask, u32 val) argument

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