| /linux-master/include/xen/interface/ |
| H A D | version.h | 55 uint32_t submap; /* OUT: 32-bit submap */
78 uint32_t len; /* IN: size of buf[]. */
|
| H A D | sched.h | 135 uint32_t id; /* watchdog ID */
136 uint32_t timeout; /* timeout */
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| /linux-master/drivers/gpu/drm/amd/pm/powerplay/smumgr/ |
| H A D | smu9_smumgr.c | 42 uint32_t mp1_fw_flags;
59 static uint32_t smu9_wait_for_response(struct pp_hwmgr *hwmgr)
62 uint32_t reg;
63 uint32_t ret;
116 uint32_t ret;
142 uint16_t msg, uint32_t parameter)
145 uint32_t ret;
166 uint32_t smu9_get_argument(struct pp_hwmgr *hwmgr)
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| /linux-master/include/xen/interface/hvm/ |
| H A D | hvm_op.h | 14 uint32_t index; /* IN */
60 uint32_t vcpu;
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| /linux-master/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn32/ |
| H A D | dcn32_smu13_driver_if.h | 47 uint32_t Spare[16];
49 uint32_t MmHubPadding[8]; // SMU internal use
|
| H A D | dcn32_clk_mgr_smu_msg.c | 50 static uint32_t dcn32_smu_wait_for_response(struct clk_mgr_internal *clk_mgr, unsigned int delay_us, unsigned int max_retries)
52 const uint32_t initial_max_retries = max_retries;
53 uint32_t reg = 0;
71 static bool dcn32_smu_send_msg_with_param(struct clk_mgr_internal *clk_mgr, uint32_t msg_id, uint32_t param_in, uint32_t *param_out)
106 static uint32_t dcn32_smu_wait_for_response_delay(struct clk_mgr_internal *clk_mgr, unsigned int delay_us, unsigned int max_retries, unsigned int *total_delay_us)
108 uint32_t reg = 0;
128 static bool dcn32_smu_send_msg_with_param_delay(struct clk_mgr_internal *clk_mgr, uint32_t msg_id, uint32_t param_i
[all...] |
| /linux-master/drivers/gpu/drm/amd/display/dc/link/protocols/ |
| H A D | link_dp_training_8b_10b.h | 46 uint32_t offset);
52 uint32_t offset);
|
| /linux-master/drivers/scsi/ |
| H A D | iscsi_tcp.h | 48 uint32_t sendpage_failures_cnt;
49 uint32_t discontiguous_hdr_cnt;
|
| /linux-master/drivers/gpu/drm/amd/pm/swsmu/inc/ |
| H A D | smu_v13_0_7_pptable.h | 146 uint32_t feature_count; //Total number of supported features
147 uint32_t setting_count; //Total number of supported settings
149 uint32_t max[SMU_13_0_7_MAX_ODSETTING]; //default maximum settings
150 uint32_t min[SMU_13_0_7_MAX_ODSETTING]; //default minimum settings
177 uint32_t golden_pp_id; //PPGen use only: PP Table ID on the Golden Data Base
178 uint32_t golden_revision; //PPGen use only: PP Table Revision on the Golden Data Base
180 uint32_t platform_caps; //POWERPLAYABLE::ulPlatformCaps
189 uint32_t reserve[45];
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| /linux-master/drivers/gpu/drm/amd/pm/inc/ |
| H A D | smu_v13_0_0_pptable.h | 146 uint32_t feature_count; //Total number of supported features
147 uint32_t setting_count; //Total number of supported settings
149 uint32_t max[SMU_13_0_0_MAX_ODSETTING]; //default maximum settings
150 uint32_t min[SMU_13_0_0_MAX_ODSETTING]; //default minimum settings
177 uint32_t golden_pp_id; //PPGen use only: PP Table ID on the Golden Data Base
178 uint32_t golden_revision; //PPGen use only: PP Table Revision on the Golden Data Base
180 uint32_t platform_caps; //POWERPLAYABLE::ulPlatformCaps
189 uint32_t reserve[45];
|
| /linux-master/drivers/gpu/drm/amd/display/dc/hwss/dcn21/ |
| H A D | dcn21_hwseq.h | 53 uint32_t backlight_pwm_u16_16,
54 uint32_t frame_ramp);
|
| /linux-master/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn35/ |
| H A D | dcn35_clk_mgr.h | 40 uint32_t ss_divider;
41 uint32_t ss_percentage[NUM_CLOCK_SOURCES];
|
| /linux-master/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn314/ |
| H A D | dcn314_clk_mgr.h | 46 uint32_t ss_divider;
47 uint32_t ss_percentage[DCN314_NUM_CLOCK_SOURCES];
|
| /linux-master/arch/arm/boot/compressed/ |
| H A D | misc.h | 15 uint32_t fdt_check_mem_start(uint32_t mem_start, const void *fdt);
|
| /linux-master/fs/xfs/scrub/ |
| H A D | rcbag.h | 22 uint32_t *next_bnop);
24 uint32_t next_bno);
|
| /linux-master/fs/dlm/ |
| H A D | config.h | 21 uint32_t comm_seq;
53 int dlm_comm_seq(int nodeid, uint32_t *seq);
|
| /linux-master/drivers/gpu/drm/msm/disp/dpu1/ |
| H A D | dpu_kms.h | 135 uint32_t pingpong_to_enc_id[PINGPONG_MAX - PINGPONG_0];
136 uint32_t mixer_to_enc_id[LM_MAX - LM_0];
137 uint32_t ctl_to_enc_id[CTL_MAX - CTL_0];
138 uint32_t dspp_to_enc_id[DSPP_MAX - DSPP_0];
139 uint32_t dsc_to_enc_id[DSC_MAX - DSC_0];
140 uint32_t cdm_to_enc_id;
175 uint32_t offset, uint32_t length, struct dpu_kms *dpu_kms);
|
| /linux-master/drivers/gpu/drm/msm/ |
| H A D | msm_gem.h | 79 uint32_t flags;
148 uint32_t handle, uint64_t *offset);
156 int msm_gem_cpu_prep(struct drm_gem_object *obj, uint32_t op, ktime_t *timeout);
159 uint32_t size, uint32_t flags, uint32_t *handle, char *name);
161 uint32_t size, uint32_t flags);
162 void *msm_gem_kernel_new(struct drm_device *dev, uint32_t size,
163 uint32_t flag
[all...] |
| /linux-master/drivers/gpu/drm/amd/display/dc/dpp/dcn35/ |
| H A D | dcn35_dpp.h | 49 DPP_REG_FIELD_LIST_DCN35(uint32_t);
58 uint32_t inst, const struct dcn3_dpp_registers *tf_regs,
|
| /linux-master/drivers/gpu/drm/amd/pm/powerplay/hwmgr/ |
| H A D | smu9_baco.c | 34 uint32_t reg, data;
55 uint32_t reg;
|
| /linux-master/include/drm/ |
| H A D | drm_lease.h | 25 uint32_t drm_lease_filter_crtcs(struct drm_file *file_priv, uint32_t crtcs);
|
| H A D | drm_plane.h | 105 uint32_t crtc_w, crtc_h;
111 uint32_t src_x;
116 uint32_t src_y;
119 uint32_t src_h, src_w;
323 uint32_t src_x, uint32_t src_y,
324 uint32_t src_w, uint32_t src_h,
550 bool (*format_mod_supported)(struct drm_plane *plane, uint32_t format,
650 uint32_t possible_crtc
[all...] |
| /linux-master/drivers/gpu/drm/vmwgfx/ |
| H A D | vmwgfx_cmd.c | 38 uint32_t fifo_min, hwversion;
45 uint32_t result;
85 uint32_t caps;
100 uint32_t max;
101 uint32_t min;
159 void vmw_fifo_ping_host(struct vmw_private *dev_priv, uint32_t reason)
187 static bool vmw_fifo_is_full(struct vmw_private *dev_priv, uint32_t bytes)
189 uint32_t max = vmw_fifo_mem_read(dev_priv, SVGA_FIFO_MAX);
190 uint32_t next_cmd = vmw_fifo_mem_read(dev_priv, SVGA_FIFO_NEXT_CMD);
191 uint32_t mi
[all...] |
| /linux-master/fs/xfs/libxfs/ |
| H A D | xfs_log_format.h | 22 typedef uint32_t xlog_tid_t;
86 uint32_t pad2; /* may as well make it 64 bits */
283 uint32_t ilf_fields; /* flags for fields logged */
286 uint32_t ilf_pad; /* pad for 64 bit boundary */
289 uint32_t ilfu_rdev; /* rdev value for dev inode*/
305 uint32_t ilf_fields; /* flags for fields logged */
310 uint32_t ilfu_rdev; /* rdev value for dev inode*/
408 uint32_t di_uid; /* owner's user id */
409 uint32_t di_gid; /* owner's group id */
410 uint32_t di_nlin
[all...] |
| /linux-master/drivers/gpu/drm/amd/display/dc/inc/ |
| H A D | link.h | 86 uint32_t connector_index; /* this will be mapped to the HPD pins */
87 uint32_t link_index; /* this is mapped to DAL display_index
133 void (*get_cur_res_map)(const struct dc *dc, uint32_t *map);
134 void (*restore_res_map)(const struct dc *dc, uint32_t *map);
144 uint32_t (*dp_link_bandwidth_kbps)(
160 struct pipe_ctx *pipe_ctx, uint32_t req_pbn);
162 struct pipe_ctx *pipe_ctx, uint32_t req_pbn);
174 uint32_t address,
176 uint32_t write_size,
178 uint32_t read_siz
[all...] |