/openbsd-current/sys/dev/pci/drm/amd/amdgpu/ |
H A D | amdgpu_umr.h | 46 u32 xcc_id; 50 u32 gpr_or_wave, se, sh, cu, wave, simd, xcc_id; 52 u32 thread, vpgr_or_sgpr;
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H A D | cik_ih.c | 62 u32 ih_cntl = RREG32(mmIH_CNTL); 63 u32 ih_rb_cntl = RREG32(mmIH_RB_CNTL); 81 u32 ih_rb_cntl = RREG32(mmIH_RB_CNTL); 82 u32 ih_cntl = RREG32(mmIH_CNTL); 110 u32 interrupt_cntl, ih_cntl, ih_rb_cntl; 188 static u32 cik_ih_get_wptr(struct amdgpu_device *adev, 191 u32 wptr, tmp; 253 u32 ring_index = ih->rptr >> 2; 357 u32 tmp = RREG32(mmSRBM_STATUS); 368 u32 tm [all...] |
H A D | amdgpu_mode.h | 250 u32 offset; 252 u32 id; 265 u32 (*vblank_get_counter)(struct amdgpu_device *adev, int crtc); 275 u32 (*hpd_get_gpio_reg)(struct amdgpu_device *adev); 280 u32 *vbl, u32 *position); 334 u32 firmware_flags; 390 u32 pll_id; 400 u32 adjusted_clock; 402 u32 pll_reference_di [all...] |
H A D | amdgpu_eeprom.c | 92 static int __amdgpu_eeprom_xfer(struct i2c_adapter *i2c_adap, u32 eeprom_addr, 138 (u32)buf_size); 181 static int amdgpu_eeprom_xfer(struct i2c_adapter *i2c_adap, u32 eeprom_addr, 227 u32 eeprom_addr, u8 *eeprom_buf, 235 u32 eeprom_addr, u8 *eeprom_buf,
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H A D | si_ih.c | 37 u32 ih_cntl = RREG32(IH_CNTL); 38 u32 ih_rb_cntl = RREG32(IH_RB_CNTL); 49 u32 ih_rb_cntl = RREG32(IH_RB_CNTL); 50 u32 ih_cntl = RREG32(IH_CNTL); 66 u32 interrupt_cntl, ih_cntl, ih_rb_cntl; 107 static u32 si_ih_get_wptr(struct amdgpu_device *adev, 110 u32 wptr, tmp; 136 u32 ring_index = ih->rptr >> 2; 222 u32 tmp = RREG32(SRBM_STATUS); 247 u32 srbm_soft_rese [all...] |
H A D | vi.c | 298 static u32 vi_pcie_rreg(struct amdgpu_device *adev, u32 reg) 301 u32 r; 311 static void vi_pcie_wreg(struct amdgpu_device *adev, u32 reg, u32 v) 323 static u32 vi_smc_rreg(struct amdgpu_device *adev, u32 reg) 326 u32 r; 335 static void vi_smc_wreg(struct amdgpu_device *adev, u32 reg, u32 [all...] |
H A D | amdgpu_object.h | 51 u32 bo_ptr_size; 52 u32 domain; 53 u32 preferred_domain; 97 u32 preferred_domains; 98 u32 allowed_domains; 128 u32 metadata_size; 177 static inline unsigned amdgpu_mem_type_to_domain(u32 mem_type) 290 void amdgpu_bo_placement_from_domain(struct amdgpu_bo *abo, u32 domain); 297 u32 domain, struct amdgpu_bo **bo_ptr, 301 u32 domai [all...] |
H A D | amdgpu_gfx.h | 111 u32 num_mec; 112 u32 num_pipe_per_mec; 113 u32 num_queue_per_pipe; 276 u32 shadow_size; 277 u32 shadow_alignment; 278 u32 csa_size; 279 u32 csa_alignment; 285 void (*select_se_sh)(struct amdgpu_device *adev, u32 se_num, 286 u32 sh_num, u32 instanc [all...] |
/openbsd-current/sys/dev/pci/drm/include/drm/ |
H A D | drm_syncobj.h | 119 u32 handle); 127 u32 handle, u64 point, u64 flags, 133 struct drm_syncobj *syncobj, u32 *handle);
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/openbsd-current/gnu/llvm/compiler-rt/lib/tsan/rtl/ |
H A D | tsan_mutexset.h | 28 u32 seq; 29 u32 count; 49 u32 seq_ = 0;
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/openbsd-current/gnu/llvm/compiler-rt/lib/sanitizer_common/tests/ |
H A D | sanitizer_stackdepot_test.cpp | 41 u32 i1 = StackDepotPut(s1); 54 u32 i1 = StackDepotPut(StackTrace()); 67 u32 i1 = StackDepotPut(s1); 68 u32 i2 = StackDepotPut(s1); 79 u32 i1 = StackDepotPut(s1); 82 u32 i2 = StackDepotPut(s2); 89 u32 i1 = StackDepotPut(s1); 92 u32 i2 = StackDepotPut(s2); 110 u32 n = 2000; 111 std::vector<u32> idx2i [all...] |
/openbsd-current/sys/dev/pci/drm/i915/ |
H A D | i915_cmd_parser.c | 115 u32 flags; 128 u32 value; 129 u32 mask; 140 u32 fixed; 141 u32 mask; 154 u32 offset; 155 u32 mask; 156 u32 step; 172 u32 offset; 173 u32 mas [all...] |
/openbsd-current/sys/dev/pci/drm/i915/display/ |
H A D | intel_vbt_defs.h | 60 u32 bdb_offset; 61 u32 aim_offset[4]; 542 u32 psr2_tp2_tp3_wakeup_time; /* 226+ */ 723 u32 panel_oui; 724 u32 dpcd_base_address; 725 u32 dpcd_idridix_control_0; 726 u32 dpcd_option_select; 727 u32 dpcd_backlight; 728 u32 ambient_light; 729 u32 backlight_scal [all...] |
/openbsd-current/sys/dev/pci/drm/i915/gvt/ |
H A D | opregion.c | 47 u32 size; 48 u32 opregion_ver; 52 u32 mboxes; 53 u32 driver_model; 54 u32 pcon; 267 int intel_vgpu_opregion_base_write_handler(struct intel_vgpu *vgpu, u32 gpa) 302 u32 __ret; \ 310 u32 __ret; \ 316 static const char *opregion_func_name(u32 func) 342 static const char *opregion_subfunc_name(u32 subfun [all...] |
H A D | gvt.h | 65 u32 max_support_vgpus; 66 u32 cfg_space_size; 67 u32 mmio_size; 68 u32 mmio_bar; 70 u32 gtt_start_offset; 71 u32 gtt_entry_size; 72 u32 gtt_entry_size_shift; 74 u32 max_surface_size; 90 u32 base; 91 u32 siz [all...] |
/openbsd-current/gnu/llvm/compiler-rt/lib/sanitizer_common/ |
H A D | sanitizer_deadlock_detector2.cpp | 24 const u32 kNoId = -1; 25 const u32 kEndId = -2; 32 u32 id; 33 u32 seq; 35 explicit Id(u32 id = 0, u32 seq = 0) 42 u32 id; 43 u32 seq; 44 u32 tid; 45 u32 stk [all...] |
H A D | sanitizer_deadlock_detector.h | 59 bool addLock(uptr lock_id, uptr current_epoch, u32 stk) { 69 u32 lock_id_short = static_cast<u32>(lock_id); 89 if (all_locks_with_contexts_[i].lock == static_cast<u32>(lock_id)) { 99 u32 findLockContext(uptr lock_id) { 101 if (all_locks_with_contexts_[i].lock == static_cast<u32>(lock_id)) 120 u32 lock; 121 u32 stk; 208 u32 findLockContext(DeadlockDetectorTLS<BV> *dtls, uptr node) { 213 void onLockAfter(DeadlockDetectorTLS<BV> *dtls, uptr cur_node, u32 st [all...] |
/openbsd-current/sys/dev/pci/drm/i915/gt/uc/ |
H A D | intel_guc_slpc.c | 57 u32 id, u32 value) 90 static u32 slpc_get_state(struct intel_guc_slpc *slpc) 96 drm_clflush_virt_range(slpc->vaddr, sizeof(u32)); 102 static int guc_action_slpc_set_param_nb(struct intel_guc *guc, u8 id, u32 value) 104 u32 request[] = { 117 static int slpc_set_param_nb(struct intel_guc_slpc *slpc, u8 id, u32 value) 126 static int guc_action_slpc_set_param(struct intel_guc *guc, u8 id, u32 value) 128 u32 request[] = { 143 u32 reques [all...] |
/openbsd-current/gnu/llvm/compiler-rt/lib/ubsan/ |
H A D | ubsan_value.h | 46 u32 Line; 47 u32 Column; 60 u32 OldColumn = __sanitizer::atomic_exchange( 61 (__sanitizer::atomic_uint32_t *)&Column, ~u32(0), 69 return Column == ~u32(0);
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/openbsd-current/sys/dev/pci/drm/radeon/ |
H A D | sumo_dpm.c | 36 static const u32 sumo_utc[SUMO_PM_NUMBER_OF_TC] = 55 static const u32 sumo_dtc[SUMO_PM_NUMBER_OF_TC] = 105 u32 local0; 106 u32 local1; 122 u32 p, u; 123 u32 xclk = radeon_get_xclk(rdev); 133 u32 p, u; 134 u32 xclk = radeon_get_xclk(rdev); 135 u32 grs = 256 * 25 / 100; 150 u32 rcu_pwr_gating_cnt [all...] |
H A D | dce6_afmt.c | 33 u32 dce6_endpoint_rreg(struct radeon_device *rdev, 34 u32 block_offset, u32 reg) 37 u32 r; 48 u32 block_offset, u32 reg, u32 v) 65 u32 offset, tmp; 131 u32 tmp = 0; 159 u32 tm [all...] |
/openbsd-current/gnu/usr.bin/gcc/gcc/testsuite/gcc.c-torture/execute/ |
H A D | 20020108-1.c | 97 typedef unsigned int u32 __attribute__((mode(SI))); typedef 100 typedef unsigned int u32 __attribute__((mode(HI))); 103 typedef unsigned int u32 __attribute__((mode(QI))); 108 u32 CAT (ashift_si_, COUNT) (u32 n) { return n << COUNT; } 113 u32 CAT (lshiftrt_si_, COUNT) (u32 n) { return n >> COUNT; } 181 != (u32) ((u32) 0xffffffff << COUNT)) abort (); 187 != (u32) ((u3 [all...] |
/openbsd-current/gnu/llvm/compiler-rt/lib/scudo/standalone/ |
H A D | common.h | 79 inline u32 getRandomU32(u32 *State) { 89 inline u32 getRandomModN(u32 *State, u32 N) { 93 template <typename T> inline void shuffle(T *A, u32 N, u32 *RandState) { 96 u32 State = *RandState; 97 for (u32 I = N - 1; I > 0; I--) 131 u32 getNumberOfCPU [all...] |
/openbsd-current/sys/dev/pci/drm/i915/gem/selftests/ |
H A D | i915_gem_coherency.c | 23 static int cpu_set(struct context *ctx, unsigned long offset, u32 v) 28 u32 *cpu; 56 static int cpu_get(struct context *ctx, unsigned long offset, u32 *v) 61 u32 *cpu; 86 static int gtt_set(struct context *ctx, unsigned long offset, u32 v) 89 u32 __iomem *map; 119 static int gtt_get(struct context *ctx, unsigned long offset, u32 *v) 122 u32 __iomem *map; 152 static int wc_set(struct context *ctx, unsigned long offset, u32 v) 154 u32 *ma [all...] |
/openbsd-current/sys/dev/pci/drm/i915/gt/ |
H A D | intel_gt_irq.c | 30 static u32 35 u32 timeout_ts; 36 u32 ident; 120 gen11_gt_identity_handler(struct intel_gt *gt, const u32 identity) 160 const u32 ident = gen11_gt_engine_identity(gt, bank, bit); 169 void gen11_gt_irq_handler(struct intel_gt *gt, const u32 master_ctl) 187 u32 dw; 264 u32 irqs = GT_RENDER_USER_INTERRUPT; 265 u32 guc_mask = intel_uc_wants_guc(>->uc) ? GUC_INTR_GUC2HOST : 0; 266 u32 gsc_mas [all...] |