Searched refs:socclk_mhz (Results 26 - 35 of 35) sorted by relevance

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/linux-master/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn30/
H A Ddcn30_clk_mgr.c144 &clk_mgr_base->bw_params->clk_table.entries[0].socclk_mhz,
/linux-master/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn32/
H A Ddcn32_clk_mgr.c196 &clk_mgr_base->bw_params->clk_table.entries[0].socclk_mhz,
198 clk_mgr_base->bw_params->dc_mode_limit.socclk_mhz = dcn30_smu_get_dc_mode_max_dpm_freq(clk_mgr, PPCLK_SOCCLK);
/linux-master/drivers/gpu/drm/amd/display/dc/dml/
H A Ddisplay_mode_vba.c381 mode_lib->vba.SOCCLK = soc->clock_limits[i].socclk_mhz;
397 mode_lib->vba.SOCCLKPerState[i] = soc->clock_limits[i].socclk_mhz;
1094 mode_lib->vba.SOCCLK = mode_lib->vba.cache_pipes[0].clks_cfg.socclk_mhz;
/linux-master/drivers/gpu/drm/amd/display/dc/dml2/
H A Ddisplay_mode_util.c623 dml_print("DML: state_bbox: socclk_mhz = %f\n", state->socclk_mhz);
H A Ddml2_wrapper.c629 out_clks.socclk_khz = (unsigned int)dml2->v20.dml_core_ctx.states.state_array[lowest_state_idx].socclk_mhz * 1000;
H A Ddisplay_mode_core_structs.h266 dml_float_t socclk_mhz; member in struct:soc_state_bounding_box_st
H A Ddisplay_mode_core.c6660 CalculateWatermarks_params->SOCCLK = mode_lib->ms.state.socclk_mhz;
8227 mode_lib->ms.SOCCLK = mode_lib->ms.state.socclk_mhz;
10061 mode_lib->ms.SOCCLK = (dml_float_t)state->socclk_mhz;
/linux-master/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn31/
H A Ddcn31_clk_mgr.c609 bw_params->clk_table.entries[i].socclk_mhz = find_clk_for_voltage(clock_table, clock_table->SocClocks, clock_table->DfPstateTable[j].Voltage);
/linux-master/drivers/gpu/drm/amd/display/dc/hwss/dcn32/
H A Ddcn32_hwseq.c721 clocks->socclk_khz = dc->clk_mgr->bw_params->clk_table.entries[0].socclk_mhz * 1000;
/linux-master/drivers/gpu/drm/amd/display/dc/dml/calcs/
H A Ddcn_calcs.c498 input->clks_cfg.socclk_mhz = v->socclk;

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