Searched refs:seqno (Results 51 - 75 of 246) sorted by relevance

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/linux-master/drivers/gpu/drm/i915/
H A Di915_trace.h275 __field(u32, seqno)
284 __entry->seqno = rq->fence.seqno;
288 TP_printk("dev=%u, engine=%u:%u, ctx=%llu, seqno=%u, flags=0x%x",
290 __entry->ctx, __entry->seqno, __entry->flags)
302 __field(u32, seqno)
311 __entry->seqno = rq->fence.seqno;
315 TP_printk("dev=%u, engine=%u:%u, ctx=%llu, seqno=%u, tail=%u",
317 __entry->ctx, __entry->seqno, __entr
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/linux-master/drivers/gpu/drm/vmwgfx/
H A Dvmwgfx_fence.c105 * a) When a new fence seqno has been submitted by the fifo code.
115 * FENCE_GOAL irq and sets the fence goal seqno to that of the next fence
117 * the subsystem makes sure the fence goal seqno is updated.
119 * The fence goal seqno irq is on as long as there are unsignaled fence
155 u32 seqno = vmw_fence_read(dev_priv); local
156 if (seqno - fence->base.seqno < VMW_FENCE_WRAP)
342 struct vmw_fence_obj *fence, u32 seqno,
348 fman->ctx, seqno);
388 * seqno i
341 vmw_fence_obj_init(struct vmw_fence_manager *fman, struct vmw_fence_obj *fence, u32 seqno, void (*destroy) (struct vmw_fence_obj *fence)) argument
468 uint32_t seqno, new_seqno; local
540 vmw_fence_create(struct vmw_fence_manager *fman, uint32_t seqno, struct vmw_fence_obj **p_fence) argument
584 vmw_user_fence_create(struct drm_file *file_priv, struct vmw_fence_manager *fman, uint32_t seqno, struct vmw_fence_obj **p_fence, uint32_t *p_handle) argument
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/linux-master/crypto/
H A Dechainiv.c32 u64 seqno; local
66 seqno = be64_to_cpu(nseqno);
77 a *= seqno;
/linux-master/drivers/gpu/drm/virtio/
H A Dvirtgpu_fence.c48 WARN_ON_ONCE(f->seqno == 0);
54 snprintf(str, size, "[%llu, %llu]", f->context, f->seqno);
90 /* This only partially initializes the fence because the seqno is
109 fence->fence_id = fence->f.seqno = ++drv->current_fence_id;
/linux-master/drivers/gpu/drm/amd/amdgpu/
H A Damdgpu_trace.h173 __field(unsigned int, seqno)
183 __entry->seqno = job->base.s_fence->finished.seqno;
187 TP_printk("sched_job=%llu, timeline=%s, context=%u, seqno=%u, ring_name=%s, num_ibs=%u",
189 __entry->seqno, __get_str(ring), __entry->num_ibs)
199 __field(unsigned int, seqno)
208 __entry->seqno = job->base.s_fence->finished.seqno;
212 TP_printk("sched_job=%llu, timeline=%s, context=%u, seqno=%u, ring_name=%s, num_ibs=%u",
214 __entry->seqno, __get_st
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/linux-master/drivers/net/ethernet/mellanox/mlx5/core/en_accel/
H A Dipsec_rxtx.c159 __be64 seqno; local
170 seqno = cpu_to_be64(xo->seq.low + ((u64)seq_hi << 32));
172 skb_store_bits(skb, iv_offset, &seqno, 8);
179 __be64 seqno; local
182 seqno = cpu_to_be64(xo->seq.low + ((u64)xo->seq.hi << 32));
184 skb_store_bits(skb, iv_offset, &seqno, 8);
/linux-master/net/dccp/
H A Dinput.c96 * Send Sync packet acknowledging P.seqno
189 u64 lswl, lawl, seqno = DCCP_SKB_CB(skb)->dccpd_seq, local
195 * If S.AWL <= P.ackno <= S.AWH and P.seqno >= S.SWL,
207 dccp_delta_seqno(dp->dccps_swl, seqno) >= 0)
208 dccp_update_gsr(sk, seqno);
218 * If LSWL <= P.seqno <= S.SWH
234 if (between48(seqno, lswl, dp->dccps_swh) &&
237 dccp_update_gsr(sk, seqno);
251 * Send Sync packet acknowledging P.seqno
262 "(LSWL(%llu) <= P.seqno(
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/linux-master/drivers/gpu/drm/xe/
H A Dxe_trace.h31 __field(int, seqno)
36 __entry->seqno = fence->seqno;
39 TP_printk("fence=%p, seqno=%d",
40 __entry->fence, __entry->seqno)
256 __field(u32, seqno)
266 __entry->seqno = xe_sched_job_seqno(job);
276 TP_printk("fence=%p, seqno=%u, guc_id=%d, batch_addr=0x%012llx, guc_state=0x%x, flags=0x%x, error=%d",
277 __entry->fence, __entry->seqno, __entry->guc_id,
352 __field(u32, seqno)
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H A Dxe_guc_submit_types.h65 u32 seqno; member in struct:pending_list_snapshot
H A Dxe_sched_job.h73 return job->fence->seqno;
H A Dxe_guc_ct.c36 u32 seqno; member in struct:g2h_fence
55 g2h_fence->seqno = ~0x0;
60 return g2h_fence->seqno == ~0x0;
540 * we use one bit of the seqno as an indicator for that and a rolling counter
547 u32 seqno = ct->fence_seqno++ & CT_SEQNO_MASK; local
550 seqno |= CT_SEQNO_UNTRACKED;
552 return seqno;
560 u16 seqno; local
594 g2h_fence->seqno = next_ct_seqno(ct, true);
596 g2h_fence->seqno,
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/linux-master/include/net/
H A Desp.h33 __be64 seqno; member in struct:esp_info
/linux-master/drivers/gpu/drm/imagination/
H A Dpvr_queue.h24 /** @seqno: Sequence number incremented each time a fence is created. */
25 atomic_t seqno; member in struct:pvr_queue_fence_ctx
/linux-master/include/linux/
H A Ddma-fence.h39 * @seqno: the sequence number of this fence inside the execution context,
93 u64 seqno; member in struct:dma_fence
130 * True if this dma_fence implementation uses 64bit seqno, false
284 spinlock_t *lock, u64 context, u64 seqno);
442 * It's recommended for seqno fences to call dma_fence_signal when the
465 * @f1: the first fence's seqno
466 * @f2: the second fence's seqno from the same context
467 * @ops: dma_fence_ops associated with the seqno
470 * from the same context, since a seqno is not common across contexts.
491 * from the same context, since a seqno i
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/linux-master/drivers/gpu/drm/v3d/
H A Dv3d_irq.c107 trace_v3d_bcl_irq(&v3d->drm, fence->seqno);
117 trace_v3d_rcl_irq(&v3d->drm, fence->seqno);
127 trace_v3d_csd_irq(&v3d->drm, fence->seqno);
164 trace_v3d_tfu_irq(&v3d->drm, fence->seqno);
/linux-master/drivers/gpu/drm/i915/gt/
H A Dintel_breadcrumbs.c117 i915_seqno_passed(rq->fence.seqno,
118 list_next_entry(rq, signal_link)->fence.seqno))
122 i915_seqno_passed(list_prev_entry(rq, signal_link)->fence.seqno,
123 rq->fence.seqno))
373 * We keep the seqno in retirement order, so we can break
390 if (i915_seqno_passed(rq->fence.seqno, it->fence.seqno))
503 rq->fence.context, rq->fence.seqno,
H A Dgen6_engine_cs.c112 * Ensure that any following seqno writes only happen
167 *cs++ = rq->fence.seqno;
297 * Ensure that any following seqno writes only happen when the render
364 *cs++ = rq->fence.seqno;
382 *cs++ = rq->fence.seqno;
403 *cs++ = rq->fence.seqno;
408 *cs++ = rq->fence.seqno;
/linux-master/drivers/net/ppp/
H A Dbsd_comp.c144 unsigned short seqno; /* sequence # of next packet */ member in struct:bsd_db
317 db->seqno = 0;
645 *wptr++ = db->seqno >> 8;
646 *wptr++ = db->seqno;
745 ++db->seqno;
875 if (seq != db->seqno)
880 db->unit, seq, db->seqno - 1);
885 ++db->seqno;
957 printk("max_ent=0x%x explen=%d seqno=%d\n",
958 max_ent, explen, db->seqno);
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/linux-master/net/smc/
H A Dsmc_cdc.h44 __be16 seqno; member in struct:smc_cdc_msg
214 peer->seqno = htons(local->seqno);
247 local->seqno = ntohs(peer->seqno);
/linux-master/net/tipc/
H A Dlink.c1029 u16 seqno = l->snd_nxt; local
1070 msg_set_seqno(hdr, seqno);
1085 seqno++;
1109 l->snd_nxt = seqno;
1162 u16 seqno = l->snd_nxt; local
1185 msg_set_seqno(hdr, seqno);
1190 seqno++;
1192 l->snd_nxt = seqno;
1359 u16 seqno; local
1394 seqno
1459 u16 expect, seqno = 0; local
1555 u16 seqno, n = 0; local
1776 u16 seqno, rcv_nxt, win_lim; local
1966 u16 pktlen, pktcnt, seqno = l->snd_nxt; local
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/linux-master/drivers/tty/hvc/
H A Dhvsi.c75 atomic_t seqno; /* HVSI packet sequence number */ member in struct:hvsi_struct
210 printk("type 0x%x, len %i, seqno %i:\n", header->type, header->len,
211 header->seqno);
287 packet.hdr.seqno = cpu_to_be16(atomic_inc_return(&hp->seqno));
311 hvsi_version_respond(hp, be16_to_cpu(query->hdr.seqno));
547 packet.hdr.seqno = cpu_to_be16(atomic_inc_return(&hp->seqno));
589 packet.hdr.seqno = cpu_to_be16(atomic_inc_return(&hp->seqno));
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/linux-master/security/selinux/
H A Davc.c569 static int avc_latest_notif_update(u32 seqno, int is_insert) argument
577 if (seqno < selinux_avc.avc_cache.latest_notif) {
578 pr_warn("SELinux: avc: seqno %d < latest_notif %d\n",
579 seqno, selinux_avc.avc_cache.latest_notif);
583 if (seqno > selinux_avc.avc_cache.latest_notif)
584 selinux_avc.avc_cache.latest_notif = seqno;
604 * sequence number @avd->seqno is not less than the latest
617 if (avc_latest_notif_update(avd->seqno, 1))
822 * @seqno : sequence number when decision was made
832 u32 tsid, u16 tclass, u32 seqno,
831 avc_update_node(u32 event, u32 perms, u8 driver, u8 xperm, u32 ssid, u32 tsid, u16 tclass, u32 seqno, struct extended_perms_decision *xpd, u32 flags) argument
952 avc_ss_reset(u32 seqno) argument
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/linux-master/drivers/gpu/drm/vgem/
H A Dvgem_fence.c58 snprintf(str, size, "%llu", fence->seqno);
65 dma_fence_is_signaled(fence) ? fence->seqno : 0);
/linux-master/drivers/gpu/drm/msm/
H A Dmsm_fence.c130 return msm_fence_completed(f->fctx, f->base.seqno);
147 max(fctx->next_deadline_fence, (uint32_t)fence->seqno);
/linux-master/drivers/gpu/drm/nouveau/
H A Dnv10_fence.c38 PUSH_MTHD(push, NV06E, SET_REFERENCE, fence->base.seqno);

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