/linux-master/drivers/gpu/drm/msm/disp/dpu1/catalog/ |
H A D | dpu_3_3_sdm630.h | 27 [DPU_CLK_CTRL_VIG0] = { .reg_off = 0x2ac, .bit_off = 0 }, 28 [DPU_CLK_CTRL_DMA0] = { .reg_off = 0x2ac, .bit_off = 8 }, 29 [DPU_CLK_CTRL_DMA1] = { .reg_off = 0x2b4, .bit_off = 8 }, 30 [DPU_CLK_CTRL_DMA2] = { .reg_off = 0x2c4, .bit_off = 8 }, 31 [DPU_CLK_CTRL_CURSOR0] = { .reg_off = 0x3a8, .bit_off = 16 },
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H A D | dpu_3_2_sdm660.h | 27 [DPU_CLK_CTRL_VIG0] = { .reg_off = 0x2ac, .bit_off = 0 }, 28 [DPU_CLK_CTRL_VIG1] = { .reg_off = 0x2b4, .bit_off = 0 }, 29 [DPU_CLK_CTRL_DMA0] = { .reg_off = 0x2ac, .bit_off = 8 }, 30 [DPU_CLK_CTRL_DMA1] = { .reg_off = 0x2b4, .bit_off = 8 }, 31 [DPU_CLK_CTRL_DMA2] = { .reg_off = 0x2c4, .bit_off = 8 }, 32 [DPU_CLK_CTRL_CURSOR0] = { .reg_off = 0x3a8, .bit_off = 16 },
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H A D | dpu_5_1_sc8180x.h | 28 [DPU_CLK_CTRL_VIG0] = { .reg_off = 0x2ac, .bit_off = 0 }, 29 [DPU_CLK_CTRL_VIG1] = { .reg_off = 0x2b4, .bit_off = 0 }, 30 [DPU_CLK_CTRL_VIG2] = { .reg_off = 0x2bc, .bit_off = 0 }, 31 [DPU_CLK_CTRL_VIG3] = { .reg_off = 0x2c4, .bit_off = 0 }, 32 [DPU_CLK_CTRL_DMA0] = { .reg_off = 0x2ac, .bit_off = 8 }, 33 [DPU_CLK_CTRL_DMA1] = { .reg_off = 0x2b4, .bit_off = 8 }, 34 [DPU_CLK_CTRL_DMA2] = { .reg_off = 0x2bc, .bit_off = 8 }, 35 [DPU_CLK_CTRL_DMA3] = { .reg_off = 0x2c4, .bit_off = 8 },
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H A D | dpu_5_0_sm8150.h | 28 [DPU_CLK_CTRL_VIG0] = { .reg_off = 0x2ac, .bit_off = 0 }, 29 [DPU_CLK_CTRL_VIG1] = { .reg_off = 0x2b4, .bit_off = 0 }, 30 [DPU_CLK_CTRL_VIG2] = { .reg_off = 0x2bc, .bit_off = 0 }, 31 [DPU_CLK_CTRL_VIG3] = { .reg_off = 0x2c4, .bit_off = 0 }, 32 [DPU_CLK_CTRL_DMA0] = { .reg_off = 0x2ac, .bit_off = 8 }, 33 [DPU_CLK_CTRL_DMA1] = { .reg_off = 0x2b4, .bit_off = 8 }, 34 [DPU_CLK_CTRL_DMA2] = { .reg_off = 0x2bc, .bit_off = 8 }, 35 [DPU_CLK_CTRL_DMA3] = { .reg_off = 0x2c4, .bit_off = 8 },
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H A D | dpu_4_0_sdm845.h | 28 [DPU_CLK_CTRL_VIG0] = { .reg_off = 0x2ac, .bit_off = 0 }, 29 [DPU_CLK_CTRL_VIG1] = { .reg_off = 0x2b4, .bit_off = 0 }, 30 [DPU_CLK_CTRL_VIG2] = { .reg_off = 0x2bc, .bit_off = 0 }, 31 [DPU_CLK_CTRL_VIG3] = { .reg_off = 0x2c4, .bit_off = 0 }, 32 [DPU_CLK_CTRL_DMA0] = { .reg_off = 0x2ac, .bit_off = 8 }, 33 [DPU_CLK_CTRL_DMA1] = { .reg_off = 0x2b4, .bit_off = 8 }, 34 [DPU_CLK_CTRL_DMA2] = { .reg_off = 0x2bc, .bit_off = 8 }, 35 [DPU_CLK_CTRL_DMA3] = { .reg_off = 0x2c4, .bit_off = 8 },
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H A D | dpu_6_3_sm6115.h | 23 [DPU_CLK_CTRL_VIG0] = { .reg_off = 0x2ac, .bit_off = 0 }, 24 [DPU_CLK_CTRL_DMA0] = { .reg_off = 0x2ac, .bit_off = 8 },
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H A D | dpu_6_5_qcm2290.h | 23 [DPU_CLK_CTRL_VIG0] = { .reg_off = 0x2ac, .bit_off = 0 }, 24 [DPU_CLK_CTRL_DMA0] = { .reg_off = 0x2ac, .bit_off = 8 },
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H A D | dpu_6_9_sm6375.h | 24 [DPU_CLK_CTRL_VIG0] = { .reg_off = 0x2ac, .bit_off = 0 }, 25 [DPU_CLK_CTRL_DMA0] = { .reg_off = 0x2ac, .bit_off = 8 },
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H A D | dpu_5_4_sm6125.h | 27 [DPU_CLK_CTRL_VIG0] = { .reg_off = 0x2ac, .bit_off = 0 }, 28 [DPU_CLK_CTRL_DMA0] = { .reg_off = 0x2ac, .bit_off = 8 }, 29 [DPU_CLK_CTRL_DMA1] = { .reg_off = 0x2b4, .bit_off = 8 },
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/linux-master/drivers/clk/meson/ |
H A D | axg-aoclk.c | 105 .reg_off = AO_RTC_ALT_CLK_CNTL0, 110 .reg_off = AO_RTC_ALT_CLK_CNTL0, 115 .reg_off = AO_RTC_ALT_CLK_CNTL1, 120 .reg_off = AO_RTC_ALT_CLK_CNTL1, 125 .reg_off = AO_RTC_ALT_CLK_CNTL0,
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H A D | gxbb-aoclk.c | 91 .reg_off = AO_RTC_ALT_CLK_CNTL0, 96 .reg_off = AO_RTC_ALT_CLK_CNTL0, 101 .reg_off = AO_RTC_ALT_CLK_CNTL1, 106 .reg_off = AO_RTC_ALT_CLK_CNTL1, 111 .reg_off = AO_RTC_ALT_CLK_CNTL0,
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H A D | gxbb.c | 91 .reg_off = HHI_MPLL_CNTL, 96 .reg_off = HHI_MPLL_CNTL, 101 .reg_off = HHI_MPLL_CNTL, 106 .reg_off = HHI_MPLL_CNTL2, 111 .reg_off = HHI_MPLL_CNTL, 116 .reg_off = HHI_MPLL_CNTL, 168 .reg_off = HHI_HDMI_PLL_CNTL, 173 .reg_off = HHI_HDMI_PLL_CNTL, 178 .reg_off = HHI_HDMI_PLL_CNTL, 183 .reg_off [all...] |
H A D | clk-cpu-dyndiv.c | 57 return regmap_update_bits(clk->map, data->div.reg_off,
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H A D | g12a.c | 36 .reg_off = HHI_FIX_PLL_CNTL0, 41 .reg_off = HHI_FIX_PLL_CNTL0, 46 .reg_off = HHI_FIX_PLL_CNTL0, 51 .reg_off = HHI_FIX_PLL_CNTL1, 56 .reg_off = HHI_FIX_PLL_CNTL0, 61 .reg_off = HHI_FIX_PLL_CNTL0, 105 .reg_off = HHI_SYS_PLL_CNTL0, 110 .reg_off = HHI_SYS_PLL_CNTL0, 115 .reg_off = HHI_SYS_PLL_CNTL0, 120 .reg_off [all...] |
/linux-master/drivers/nvmem/ |
H A D | imx-ocotp-ele.c | 29 u32 reg_off; member in struct:ocotp_devtype_data 67 void __iomem *reg = priv->base + priv->data->reg_off; 144 .reg_off = 0x8000,
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/linux-master/drivers/net/ethernet/cavium/liquidio/ |
H A D | octeon_device.h | 740 #define octeon_write_csr(oct_dev, reg_off, value) \ 741 writel(value, (oct_dev)->mmio[0].hw_addr + (reg_off)) 743 #define octeon_write_csr64(oct_dev, reg_off, val64) \ 744 writeq(val64, (oct_dev)->mmio[0].hw_addr + (reg_off)) 746 #define octeon_read_csr(oct_dev, reg_off) \ 747 readl((oct_dev)->mmio[0].hw_addr + (reg_off)) 749 #define octeon_read_csr64(oct_dev, reg_off) \ 750 readq((oct_dev)->mmio[0].hw_addr + (reg_off))
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/linux-master/drivers/staging/vt6656/ |
H A D | usbpipe.h | 56 int vnt_control_in_u8(struct vnt_private *priv, u8 reg, u8 reg_off, u8 *data);
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/linux-master/drivers/thermal/ |
H A D | loongson2_thermal.c | 54 int reg_off = data->chip_data->thermal_sensor_sel * 2; local 59 writew(reg_ctrl, data->ctrl_reg + ctrl_reg + reg_off);
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/linux-master/tools/testing/selftests/kvm/lib/aarch64/ |
H A D | vgic.c | 131 uint64_t reg_off) 135 uint64_t attr = reg_off + reg * 4; 130 vgic_poke_irq(int gic_fd, uint32_t intid, struct kvm_vcpu *vcpu, uint64_t reg_off) argument
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/linux-master/arch/x86/kvm/ |
H A D | lapic.h | 174 static inline u32 __kvm_lapic_get_reg(char *regs, int reg_off) argument 176 return *((u32 *) (regs + reg_off)); 179 static inline u32 kvm_lapic_get_reg(struct kvm_lapic *apic, int reg_off) argument 181 return __kvm_lapic_get_reg(apic->regs, reg_off);
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/linux-master/tools/lib/bpf/ |
H A D | usdt.bpf.h | 45 short reg_off; member in struct:__bpf_usdt_arg_spec 151 * record offsetof(struct pt_regs, <regname>) in arg_spec->reg_off. 153 err = bpf_probe_read_kernel(&val, sizeof(val), (void *)ctx + arg_spec->reg_off); 165 err = bpf_probe_read_kernel(&val, sizeof(val), (void *)ctx + arg_spec->reg_off);
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/linux-master/sound/soc/xilinx/ |
H A D | xlnx_i2s.c | 94 u32 reg_off, chan_id; local 120 reg_off = I2S_CH0_OFFSET + ((chan_id - 1) * 4); 121 writel(chan_id, drv_data->base + reg_off);
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/linux-master/drivers/accel/habanalabs/goya/ |
H A D | goya.c | 1091 u32 reg_off = dma_id * (mmDMA_QM_1_PQ_PI - mmDMA_QM_0_PQ_PI); local 1104 WREG32(mmDMA_QM_0_PQ_BASE_LO + reg_off, lower_32_bits(bus_address)); 1105 WREG32(mmDMA_QM_0_PQ_BASE_HI + reg_off, upper_32_bits(bus_address)); 1107 WREG32(mmDMA_QM_0_PQ_SIZE + reg_off, ilog2(HL_QUEUE_LENGTH)); 1108 WREG32(mmDMA_QM_0_PQ_PI + reg_off, 0); 1109 WREG32(mmDMA_QM_0_PQ_CI + reg_off, 0); 1111 WREG32(mmDMA_QM_0_CP_MSG_BASE0_ADDR_LO + reg_off, mtr_base_lo); 1112 WREG32(mmDMA_QM_0_CP_MSG_BASE0_ADDR_HI + reg_off, mtr_base_hi); 1113 WREG32(mmDMA_QM_0_CP_MSG_BASE1_ADDR_LO + reg_off, so_base_lo); 1114 WREG32(mmDMA_QM_0_CP_MSG_BASE1_ADDR_HI + reg_off, so_base_h 1140 u32 reg_off = dma_id * (mmDMA_CH_1_CFG1 - mmDMA_CH_0_CFG1); local 1940 u32 reg_off = tpc_id * (mmTPC1_QM_PQ_PI - mmTPC0_QM_PQ_PI); local 1989 u32 reg_off = tpc_id * (mmTPC1_CMDQ_CQ_CFG1 - mmTPC0_CMDQ_CQ_CFG1); local [all...] |
/linux-master/drivers/pinctrl/spear/ |
H A D | pinctrl-plgpio.c | 85 u32 reg_off = REG_OFFSET(0, reg, pin); local 88 regmap_read(regmap, reg_off, &val); 96 u32 reg_off = REG_OFFSET(0, reg, pin); local 100 regmap_update_bits(regmap, reg_off, mask, mask); 106 u32 reg_off = REG_OFFSET(0, reg, pin); local 110 regmap_update_bits(regmap, reg_off, mask, 0); 330 u32 reg_off; local 347 reg_off = REG_OFFSET(0, plgpio->regs.eit, offset); 348 regmap_read(plgpio->regmap, reg_off, &val); 352 regmap_write(plgpio->regmap, reg_off, va [all...] |
/linux-master/drivers/gpu/drm/msm/disp/dpu1/ |
H A D | dpu_hw_util.c | 91 u32 reg_off, 98 name, reg_off, val); 99 writel_relaxed(val, c->blk_addr + reg_off); 102 int dpu_reg_read(struct dpu_hw_blk_reg_map *c, u32 reg_off) argument 104 return readl_relaxed(c->blk_addr + reg_off); 547 reg_val = DPU_REG_READ(c, clk_ctrl_reg->reg_off); 554 DPU_REG_WRITE(c, clk_ctrl_reg->reg_off, new_val); 90 dpu_reg_write(struct dpu_hw_blk_reg_map *c, u32 reg_off, u32 val, const char *name) argument
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