Searched refs:prate (Results 51 - 75 of 142) sorted by relevance

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/linux-master/drivers/clk/imx/
H A Dclk-composite-8m.c78 unsigned long *prate)
83 imx8m_clk_composite_compute_dividers(rate, *prate,
85 rate = DIV_ROUND_UP(*prate, prediv_value);
76 imx8m_clk_composite_divider_round_rate(struct clk_hw *hw, unsigned long rate, unsigned long *prate) argument
H A Dclk-cpu.c34 unsigned long *prate)
33 clk_cpu_round_rate(struct clk_hw *hw, unsigned long rate, unsigned long *prate) argument
H A Dclk-frac-pll.c123 unsigned long *prate)
125 u64 parent_rate = *prate;
122 clk_pll_round_rate(struct clk_hw *hw, unsigned long rate, unsigned long *prate) argument
H A Dclk-composite-93.c95 imx93_clk_composite_divider_round_rate(struct clk_hw *hw, unsigned long rate, unsigned long *prate) argument
97 return clk_divider_ops.round_rate(hw, rate, prate);
H A Dclk-busy.c50 unsigned long *prate)
54 return busy->div_ops->round_rate(&busy->div.hw, rate, prate);
49 clk_busy_divider_round_rate(struct clk_hw *hw, unsigned long rate, unsigned long *prate) argument
H A Dclk-pllv4.c99 unsigned long *prate)
102 unsigned long parent_rate = *prate;
98 clk_pllv4_round_rate(struct clk_hw *hw, unsigned long rate, unsigned long *prate) argument
H A Dclk-sscg-pll.c265 uint64_t prate,
279 if (prate == rate) {
286 ret = clk_sscg_pll2_find_setup(setup, &temp_setup, prate);
289 ret = clk_sscg_pll1_find_setup(setup, &temp_setup, prate);
264 clk_sscg_pll_find_setup(struct clk_sscg_pll_setup *setup, uint64_t prate, uint64_t rate, int try_bypass) argument
/linux-master/include/trace/events/
H A Dclk.h278 __field(unsigned long, prate )
286 __entry->prate = req->best_parent_rate;
293 (unsigned long)__entry->prate)
/linux-master/drivers/clk/
H A Dclk-si521xx.c168 unsigned long *prate)
173 *prate = clk_hw_round_rate(clk_hw_get_parent(hw), best_parent);
175 return (*prate / SI521XX_DIFF_DIV) * SI521XX_DIFF_MULT;
167 si521xx_diff_round_rate(struct clk_hw *hw, unsigned long rate, unsigned long *prate) argument
H A Dclk-fixed-factor.c34 unsigned long *prate)
42 *prate = clk_hw_round_rate(clk_hw_get_parent(hw), best_parent);
45 return (*prate / fix->div) * fix->mult;
33 clk_factor_round_rate(struct clk_hw *hw, unsigned long rate, unsigned long *prate) argument
H A Dclk-loongson1.c97 unsigned long *prate)
102 return divider_round_rate(hw, rate, prate, d->table,
96 ls1x_divider_round_rate(struct clk_hw *hw, unsigned long rate, unsigned long *prate) argument
/linux-master/arch/arm/mach-sa1100/
H A Dclock.c72 unsigned long prate)
71 clk_mpll_recalc_rate(struct clk_hw *hw, unsigned long prate) argument
/linux-master/drivers/clk/spear/
H A Dclk.h106 typedef unsigned long (*clk_calc_rate)(struct clk_hw *hw, unsigned long prate,
/linux-master/drivers/clk/sophgo/
H A Dclk-cv18xx-pll.c48 unsigned long prate, unsigned long *rate,
61 tmp = ipll_calc_rate(prate, pre, div, post);
284 unsigned long prate,
300 tmp = fpll_find_synthesizer(prate, trate,
47 ipll_find_rate(const struct cv1800_clk_pll_limit *limit, unsigned long prate, unsigned long *rate, u32 *value) argument
282 fpll_find_rate(struct cv1800_clk_pll *pll, const struct cv1800_clk_pll_limit *limit, unsigned long prate, unsigned long *rate, u32 *value, u32 *ssc_syn_set) argument
/linux-master/drivers/video/fbdev/omap2/omapfb/dss/
H A Ddss.c517 unsigned long prate; local
537 prate = clk_get_rate(dss.parent_clk);
541 fckd_start = min(prate * m / fck_min, fckd_hw_max);
542 fckd_stop = max(DIV_ROUND_UP(prate * m, fck_hw_max), 1ul);
545 fck = DIV_ROUND_UP(prate, fckd) * m;
580 unsigned long max_dss_fck, prate; local
590 prate = clk_get_rate(dss.parent_clk);
592 fck_div = DIV_ROUND_UP(prate * dss.feat->dss_fck_multiplier,
594 fck = DIV_ROUND_UP(prate, fck_div) * dss.feat->dss_fck_multiplier;
/linux-master/drivers/clk/st/
H A Dclkgen-fsyn.c380 unsigned long *prate)
384 if (clk_fs660c32_vco_get_params(*prate, rate, &params))
387 clk_fs660c32_vco_get_rate(*prate, &params, &rate);
776 unsigned long prate, struct stm_fs *params)
787 if (!clk_fs_get_params(prate, drate, params))
788 clk_fs_get_rate(prate, params, &rate);
818 unsigned long *prate)
822 rate = quadfs_find_best_rate(hw, rate, *prate, &params);
378 quadfs_pll_fs660c32_round_rate(struct clk_hw *hw, unsigned long rate, unsigned long *prate) argument
775 quadfs_find_best_rate(struct clk_hw *hw, unsigned long drate, unsigned long prate, struct stm_fs *params) argument
817 quadfs_round_rate(struct clk_hw *hw, unsigned long rate, unsigned long *prate) argument
/linux-master/drivers/clk/meson/
H A Dclk-regmap.c60 unsigned long prate)
74 return divider_recalc_rate(hw, prate, val, div->table, div->flags,
59 clk_regmap_div_recalc_rate(struct clk_hw *hw, unsigned long prate) argument
/linux-master/drivers/gpu/drm/imx/ipuv3/
H A Dimx-tve.c368 unsigned long *prate)
372 div = *prate / rate;
374 return *prate / 4;
376 return *prate / 2;
377 return *prate;
367 clk_tve_di_round_rate(struct clk_hw *hw, unsigned long rate, unsigned long *prate) argument
/linux-master/drivers/gpu/drm/omapdrm/dss/
H A Ddss.c606 unsigned long prate; local
626 prate = clk_get_rate(dss->parent_clk);
630 fckd_start = min(prate * m / fck_min, fckd_hw_max);
631 fckd_stop = max(DIV_ROUND_UP(prate * m, fck_hw_max), 1ul);
634 fck = DIV_ROUND_UP(prate, fckd) * m;
673 unsigned long max_dss_fck, prate; local
683 prate = clk_get_rate(dss->parent_clk);
685 fck_div = DIV_ROUND_UP(prate * dss->feat->dss_fck_multiplier,
687 fck = DIV_ROUND_UP(prate, fck_div)
/linux-master/drivers/clk/mediatek/
H A Dclk-pll.c204 unsigned long *prate)
210 mtk_pll_calc_values(pll, &pcw, &postdiv, rate, *prate);
212 return __mtk_pll_recalc_rate(pll, *prate, pcw, postdiv);
203 mtk_pll_round_rate(struct clk_hw *hw, unsigned long rate, unsigned long *prate) argument
/linux-master/drivers/clk/ti/
H A Ddivider.c227 unsigned long *prate)
230 div = ti_clk_divider_bestdiv(hw, rate, prate);
232 return DIV_ROUND_UP(*prate, div);
226 ti_clk_divider_round_rate(struct clk_hw *hw, unsigned long rate, unsigned long *prate) argument
/linux-master/drivers/clk/hisilicon/
H A Dclk-hi3660-stub.c71 unsigned long *prate)
70 hi3660_stub_clk_round_rate(struct clk_hw *hw, unsigned long rate, unsigned long *prate) argument
/linux-master/drivers/phy/mediatek/
H A Dphy-mtk-mipi-dsi-mt8183.c101 unsigned long *prate)
100 mtk_mipi_tx_pll_round_rate(struct clk_hw *hw, unsigned long rate, unsigned long *prate) argument
/linux-master/drivers/clk/nxp/
H A Dclk-lpc18xx-cgu.c374 unsigned long *prate)
378 if (*prate < rate) {
383 m = DIV_ROUND_UP_ULL(*prate, rate * 2);
389 return 2 * *prate * m;
373 lpc18xx_pll0_round_rate(struct clk_hw *hw, unsigned long rate, unsigned long *prate) argument
/linux-master/drivers/clk/microchip/
H A Dclk-mpfs-ccc.c73 static unsigned long mpfs_ccc_pll_recalc_rate(struct clk_hw *hw, unsigned long prate) argument
85 return prate * mult / (ref_div * MPFS_CCC_FIXED_DIV);

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