Searched refs:num_states (Results 26 - 50 of 57) sorted by relevance

123

/linux-master/drivers/gpu/drm/amd/display/dc/dml/dcn20/
H A Ddisplay_mode_vba_20.c1260 mode_lib->vba.soc.clock_limits[mode_lib->vba.soc.num_states].dispclk_mhz,
2598 for (k = 0; k <= mode_lib->vba.soc.num_states; k++)
3441 for (i = 0; i <= mode_lib->vba.soc.num_states; i++) {
3523 for (i = 0; i <= mode_lib->vba.soc.num_states; i++) {
3874 for (i = 0; i <= mode_lib->vba.soc.num_states; i++) {
3889 && i == mode_lib->vba.soc.num_states)
3896 && i == mode_lib->vba.soc.num_states)
3970 if (i != mode_lib->vba.soc.num_states) {
4002 for (i = 0; i <= mode_lib->vba.soc.num_states; i++) {
4019 for (i = 0; i <= mode_lib->vba.soc.num_states;
[all...]
/linux-master/drivers/gpu/drm/amd/display/amdgpu_dm/
H A Damdgpu_dm_pp_smu.c709 unsigned int *clock_values_in_khz, unsigned int *num_states)
717 num_states);
708 pp_nv_get_uclk_dpm_states(struct pp_smu *pp, unsigned int *clock_values_in_khz, unsigned int *num_states) argument
/linux-master/drivers/gpu/drm/amd/display/dc/dml/dcn21/
H A Ddisplay_mode_vba_21.c1644 mode_lib->vba.soc.clock_limits[mode_lib->vba.soc.num_states - 1].dispclk_mhz,
3674 for (i = 0; i <= mode_lib->vba.soc.num_states; i++) {
3716 for (i = 0; i <= mode_lib->vba.soc.num_states; i++) {
4070 for (i = 0; i <= mode_lib->vba.soc.num_states; i++) {
4072 mode_lib->vba.MaxDispclk[mode_lib->vba.soc.num_states],
4094 && i == mode_lib->vba.soc.num_states)
4101 && i == mode_lib->vba.soc.num_states)
4178 if (i != mode_lib->vba.soc.num_states) {
4210 for (i = 0; i <= mode_lib->vba.soc.num_states; i++) {
4227 for (i = 0; i <= mode_lib->vba.soc.num_states;
[all...]
/linux-master/drivers/gpu/drm/amd/display/dc/dml/
H A Ddisplay_mode_lib.c291 for (i = mode_lib->vba.soc.num_states; i >= 0; i--) {
H A Ddisplay_mode_structs.h184 * @num_states: It represents the total of Display Power Management
187 unsigned int num_states; member in struct:_vcs_dpi_soc_bounding_box_st
H A Ddisplay_mode_vba.c376 for (i = 0; i < mode_lib->vba.soc.num_states; i++)
394 for (i = 0; i <= mode_lib->vba.soc.num_states; i++) {
/linux-master/include/linux/regulator/
H A Ddriver.h480 * @num_states: Amount of associated regulators.
495 int num_states; member in struct:regulator_irq_data
/linux-master/drivers/gpu/drm/amd/display/dc/dml/dcn30/
H A Ddisplay_mode_vba_30.c1990 v->soc.clock_limits[mode_lib->soc.num_states - 1].dispclk_mhz,
3556 start_state = v->soc.num_states - 1;
3858 for (i = start_state; i < v->soc.num_states; i++) {
3867 if ((v->PlaneRequiredDISPCLKWithoutODMCombine >= v->MaxDispclk[i] && v->MaxDispclk[i] == v->MaxDispclk[mode_lib->soc.num_states - 1]
3868 && v->MaxDppclk[i] == v->MaxDppclk[mode_lib->soc.num_states - 1])) {
3873 if ((v->PlaneRequiredDISPCLKWithODMCombine2To1 >= v->MaxDispclk[i] && v->MaxDispclk[i] == v->MaxDispclk[mode_lib->soc.num_states - 1]
3874 && v->MaxDppclk[i] == v->MaxDppclk[mode_lib->soc.num_states - 1])) {
3879 if ((v->PlaneRequiredDISPCLKWithODMCombine4To1 >= v->MaxDispclk[i] && v->MaxDispclk[i] == v->MaxDispclk[mode_lib->soc.num_states - 1]
3880 && v->MaxDppclk[i] == v->MaxDppclk[mode_lib->soc.num_states - 1])) {
3988 if (!(v->MaxDispclk[i] == v->MaxDispclk[v->soc.num_states
[all...]
H A Ddcn30_fpu.c138 .num_states = 1,
574 for (i = 0; i < dc->dml.soc.num_states; i++) {
652 for (i = 0; i < dcn3_0_soc.num_states; i++) {
/linux-master/drivers/gpu/drm/amd/display/dc/dml/dcn314/
H A Ddisplay_mode_vba_314.c2152 v->soc.clock_limits[v->soc.num_states - 1].dispclk_mhz,
4163 for (i = 0; i < v->soc.num_states; i++) {
4173 && v->MaxDispclk[i] == v->MaxDispclk[v->soc.num_states - 1]
4174 && v->MaxDppclk[i] == v->MaxDppclk[v->soc.num_states - 1])) {
4181 && v->MaxDispclk[i] == v->MaxDispclk[v->soc.num_states - 1]
4182 && v->MaxDppclk[i] == v->MaxDppclk[v->soc.num_states - 1])) {
4189 && v->MaxDispclk[i] == v->MaxDispclk[v->soc.num_states - 1]
4190 && v->MaxDppclk[i] == v->MaxDppclk[v->soc.num_states - 1])) {
4321 if (!(v->MaxDispclk[i] == v->MaxDispclk[v->soc.num_states - 1]
4322 && v->MaxDppclk[i] == v->MaxDppclk[v->soc.num_states
[all...]
/linux-master/drivers/gpu/drm/amd/display/dc/dml/dcn31/
H A Ddisplay_mode_vba_31.c2131 v->soc.clock_limits[v->soc.num_states - 1].dispclk_mhz,
4070 for (i = 0; i < v->soc.num_states; i++) {
4080 && v->MaxDispclk[i] == v->MaxDispclk[v->soc.num_states - 1]
4081 && v->MaxDppclk[i] == v->MaxDppclk[v->soc.num_states - 1])) {
4088 && v->MaxDispclk[i] == v->MaxDispclk[v->soc.num_states - 1]
4089 && v->MaxDppclk[i] == v->MaxDppclk[v->soc.num_states - 1])) {
4096 && v->MaxDispclk[i] == v->MaxDispclk[v->soc.num_states - 1]
4097 && v->MaxDppclk[i] == v->MaxDppclk[v->soc.num_states - 1])) {
4231 if (!(v->MaxDispclk[i] == v->MaxDispclk[v->soc.num_states - 1]
4232 && v->MaxDppclk[i] == v->MaxDppclk[v->soc.num_states
[all...]
/linux-master/drivers/gpu/drm/amd/display/dc/resource/dcn21/
H A Ddcn21_resource.c804 if (vlevel > context->bw_ctx.dml.soc.num_states) {
815 if (vlevel > context->bw_ctx.dml.soc.num_states)
904 context->bw_ctx.dml.vba.ValidationStatus[context->bw_ctx.dml.vba.soc.num_states] =
/linux-master/net/netfilter/ipvs/
H A Dip_vs_proto_udp.c485 .num_states = IP_VS_UDP_S_LAST,
H A Dip_vs_proto_sctp.c579 .num_states = IP_VS_SCTP_S_LAST,
H A Dip_vs_sync.c1001 if (state >= pp->num_states) {
1160 if (state >= pp->num_states) {
H A Dip_vs_proto_tcp.c728 .num_states = IP_VS_TCP_S_LAST,
/linux-master/drivers/gpu/drm/amd/display/dc/resource/dcn301/
H A Ddcn301_resource.c1331 if (loaded_bb->num_states == 1) {
1339 } else if (loaded_bb->num_states > 1) {
1340 for (i = 0; i < 4 && i < loaded_bb->num_states; i++) {
/linux-master/drivers/gpu/drm/amd/pm/inc/
H A Damdgpu_dpm.h598 unsigned int *num_states);
/linux-master/drivers/gpu/drm/amd/pm/
H A Damdgpu_dpm.c1862 unsigned int *num_states)
1873 num_states);
1860 amdgpu_dpm_get_uclk_dpm_states(struct amdgpu_device *adev, unsigned int *clock_values_in_khz, unsigned int *num_states) argument
/linux-master/drivers/gpu/drm/amd/display/dc/resource/dcn201/
H A Ddcn201_resource.c197 .num_states = 4,
/linux-master/drivers/gpu/drm/amd/pm/swsmu/inc/
H A Damdgpu_smu.h810 * &num_states: Elements in &clocks_in_khz.
812 int (*get_uclk_dpm_states)(struct smu_context *smu, uint32_t *clocks_in_khz, uint32_t *num_states);
/linux-master/drivers/gpu/drm/amd/include/
H A Dkgd_pp_interface.h443 unsigned int *num_states);
/linux-master/sound/soc/
H A Dsoc-pcm.c3052 int num_states)
3065 for (i = 0; i < num_states; i++) {
3048 snd_soc_dpcm_check_state(struct snd_soc_pcm_runtime *fe, struct snd_soc_pcm_runtime *be, int stream, const enum snd_soc_dpcm_state *states, int num_states) argument
/linux-master/include/net/
H A Dip_vs.h480 u16 num_states; member in struct:ip_vs_protocol
/linux-master/drivers/gpu/drm/amd/pm/swsmu/smu11/
H A Dnavi10_ppt.c2249 static int navi10_get_uclk_dpm_states(struct smu_context *smu, uint32_t *clocks_in_khz, uint32_t *num_states) argument
2257 if (!clocks_in_khz || !num_states || !table_context->driver_pptable)
2267 *num_states = num_discrete_levels;

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