/linux-master/arch/loongarch/include/asm/ |
H A D | irqflags.h | 18 "csrxchg %[val], %[mask], %[reg]\n\t" 20 : [mask] "r" (CSR_CRMD_IE), [reg] "i" (LOONGARCH_CSR_CRMD) 28 "csrxchg %[val], %[mask], %[reg]\n\t" 30 : [mask] "r" (CSR_CRMD_IE), [reg] "i" (LOONGARCH_CSR_CRMD) 38 "csrxchg %[val], %[mask], %[reg]\n\t" 40 : [mask] "r" (CSR_CRMD_IE), [reg] "i" (LOONGARCH_CSR_CRMD) 48 "csrxchg %[val], %[mask], %[reg]\n\t" 50 : [mask] "r" (CSR_CRMD_IE), [reg] "i" (LOONGARCH_CSR_CRMD)
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/linux-master/drivers/crypto/intel/qat/qat_common/ |
H A D | qat_crypto.h | 56 u32 mask = ~hw_device->accel_capabilities_mask; local 58 if (mask & ADF_ACCEL_CAPABILITIES_CRYPTO_SYMMETRIC) 60 if (mask & ADF_ACCEL_CAPABILITIES_CRYPTO_ASYMMETRIC) 62 if (mask & ADF_ACCEL_CAPABILITIES_AUTHENTICATION)
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H A D | qat_compression.h | 29 u32 mask = ~hw_device->accel_capabilities_mask; local 31 if (mask & ADF_ACCEL_CAPABILITIES_COMPRESSION)
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/linux-master/drivers/iio/accel/ |
H A D | st_accel_core.c | 128 .mask = 0xf0, 142 .mask = 0xf0, 147 .mask = ST_SENSORS_DEFAULT_AXIS_MASK, 151 .mask = 0x30, 177 .mask = 0x80, 182 .mask = 0x10, 188 .mask = 0x07, 210 .mask = 0x18, 220 .mask = 0xe0, 226 .mask 1184 st_accel_read_raw(struct iio_dev *indio_dev, struct iio_chan_spec const *ch, int *val, int *val2, long mask) argument 1213 st_accel_write_raw(struct iio_dev *indio_dev, struct iio_chan_spec const *chan, int val, int val2, long mask) argument [all...] |
/linux-master/arch/x86/kernel/apic/ |
H A D | hw_nmi.c | 34 static void nmi_raise_cpu_backtrace(cpumask_t *mask) argument 36 __apic_send_IPI_mask(mask, NMI_VECTOR); 39 void arch_trigger_cpumask_backtrace(const cpumask_t *mask, int exclude_cpu) argument 41 nmi_trigger_cpumask_backtrace(mask, exclude_cpu,
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/linux-master/drivers/gpu/drm/arm/display/include/ |
H A D | malidp_utils.h | 13 #define has_bit(nr, mask) (BIT(nr) & (mask)) 14 #define has_bits(bits, mask) (((bits) & (mask)) == (bits))
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/linux-master/drivers/irqchip/ |
H A D | irq-xtensa-mx.c | 72 unsigned int mask = 1u << d->hwirq; local 74 if (mask & (XCHAL_INTTYPE_MASK_EXTERN_EDGE | 83 mask = __this_cpu_read(cached_irq_mask) & ~mask; 84 __this_cpu_write(cached_irq_mask, mask); 85 xtensa_set_sr(mask, intenable); 90 unsigned int mask = 1u << d->hwirq; local 92 if (mask & (XCHAL_INTTYPE_MASK_EXTERN_EDGE | 101 mask |= __this_cpu_read(cached_irq_mask); 102 __this_cpu_write(cached_irq_mask, mask); 123 unsigned int mask = 1u << d->hwirq; local 135 unsigned mask = 1u << cpu; local [all...] |
/linux-master/arch/m68k/include/asm/ |
H A D | nettel.h | 56 static __inline__ void mcf_setppdata(unsigned int mask, unsigned int bits) argument 60 ppdata = (ppdata & ~mask) | bits; 93 static __inline__ void mcf_setppdata(unsigned int mask, unsigned int bits) argument 95 writew((readw(MCFSIM_PBDAT) & ~mask) | bits, MCFSIM_PBDAT);
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/linux-master/drivers/mfd/ |
H A D | max77541.c | 20 { .mask = MAX77541_BIT_INT_SRC_TOPSYS }, 21 { .mask = MAX77541_BIT_INT_SRC_BUCK }, 34 { .mask = MAX77541_BIT_TOPSYS_INT_TJ_120C }, 35 { .mask = MAX77541_BIT_TOPSYS_INT_TJ_140C }, 36 { .mask = MAX77541_BIT_TOPSYS_INT_TSHDN }, 37 { .mask = MAX77541_BIT_TOPSYS_INT_UVLO }, 38 { .mask = MAX77541_BIT_TOPSYS_INT_ALT_SWO }, 39 { .mask = MAX77541_BIT_TOPSYS_INT_EXT_FREQ_DET }, 52 { .mask = MAX77541_BIT_BUCK_INT_M1_POK_FLT }, 53 { .mask [all...] |
H A D | palmas.c | 48 .mask = TPS65917_RESERVED, 51 .mask = TPS65917_INT1_STATUS_PWRON, 54 .mask = TPS65917_INT1_STATUS_LONG_PRESS_KEY, 57 .mask = TPS65917_RESERVED, 60 .mask = TPS65917_INT1_STATUS_PWRDOWN, 63 .mask = TPS65917_INT1_STATUS_HOTDIE, 66 .mask = TPS65917_INT1_STATUS_VSYS_MON, 69 .mask = TPS65917_RESERVED, 73 .mask = TPS65917_RESERVED, 77 .mask [all...] |
/linux-master/drivers/staging/media/atomisp/pci/css_2401_system/host/ |
H A D | isys_irq_local.h | 25 hrt_data mask; member in struct:isys_irqc_state_s
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/linux-master/tools/perf/arch/arm64/util/ |
H A D | machine.c | 17 opts->sample_user_regs |= sample_reg_masks[PERF_REG_ARM64_LR].mask;
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/linux-master/arch/alpha/kernel/ |
H A D | sys_sable.c | 39 /* Note mask bit is true for DISABLED irqs. */ 42 void (*update_irq_hw)(unsigned long bit, unsigned long mask); 93 sable_update_irq_hw(unsigned long bit, unsigned long mask) argument 99 mask >>= 16; 102 mask >>= 8; 105 outb(mask, port); 143 34, 33, 32, 12, 35, 36, 1, 6, /* mask 0-7 */ 144 3, 7, -1, -1, 5, -1, -1, 4, /* mask 8-15 */ 145 9, 10, 11, -1, -1, 14, 15, -1, /* mask 16-23 */ 221 unsigned long bit, mask; local 237 unsigned long bit, mask; local 253 unsigned long bit, mask; local [all...] |
/linux-master/drivers/acpi/arm64/ |
H A D | dma.c | 10 u64 end, mask; local 17 * coherent mask if not, but we'll no longer do so quietly. 20 dev_warn(dev, "DMA mask not set\n"); 39 * Limit coherent and dma mask based on size retrieved from 42 mask = DMA_BIT_MASK(ilog2(end) + 1); 44 dev->coherent_dma_mask = min(dev->coherent_dma_mask, mask); 45 *dev->dma_mask = min(*dev->dma_mask, mask);
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/linux-master/drivers/gpu/drm/i915/gt/ |
H A D | intel_gt_pm_irq.c | 17 u32 mask = gt->pm_imr; local 22 mask <<= 16; /* pm is in upper half */ 29 intel_uncore_write(uncore, reg, mask); 52 void gen6_gt_pm_unmask_irq(struct intel_gt *gt, u32 mask) argument 54 gen6_gt_pm_update_irq(gt, mask, mask); 57 void gen6_gt_pm_mask_irq(struct intel_gt *gt, u32 mask) argument 59 gen6_gt_pm_update_irq(gt, mask, 0); 78 u32 mask = gt->pm_ier; local 83 mask << [all...] |
/linux-master/include/crypto/internal/ |
H A D | cipher.h | 47 * @mask: specifies the mask for the cipher 57 u32 type, u32 mask) 61 mask |= CRYPTO_ALG_TYPE_MASK; 63 return __crypto_cipher_cast(crypto_alloc_base(alg_name, type, mask)); 85 * @mask: specifies the mask for the cipher 90 static inline int crypto_has_cipher(const char *alg_name, u32 type, u32 mask) argument 94 mask |= CRYPTO_ALG_TYPE_MASK; 96 return crypto_has_alg(alg_name, type, mask); 56 crypto_alloc_cipher(const char *alg_name, u32 type, u32 mask) argument 185 crypto_grab_cipher(struct crypto_cipher_spawn *spawn, struct crypto_instance *inst, const char *name, u32 type, u32 mask) argument 210 u32 mask = CRYPTO_ALG_TYPE_MASK; local [all...] |
/linux-master/drivers/net/ethernet/ti/icssg/ |
H A D | icssg_mii_cfg.c | 72 u32 val, mask, shift; local 74 mask = mii == ICSS_MII0 ? ICSSG_CFG_MII0_MODE : ICSSG_CFG_MII1_MODE; 82 regmap_update_bits(miig_rt, ICSSG_CFG_OFFSET, mask, val); 86 u32 icssg_rgmii_cfg_get_bitfield(struct regmap *miig_rt, u32 mask, u32 shift) argument 91 val &= mask; 99 u32 shift = RGMII_CFG_SPEED_MII0_SHIFT, mask = RGMII_CFG_SPEED_MII0; local 103 mask = RGMII_CFG_SPEED_MII1; 106 return icssg_rgmii_cfg_get_bitfield(miig_rt, mask, shift); 112 u32 mask = RGMII_CFG_FULLDUPLEX_MII0; local 116 mask [all...] |
/linux-master/arch/arm64/include/asm/vdso/ |
H A D | vsyscall.h | 27 vdata[CS_HRES_COARSE].mask = VDSO_PRECISION_MASK; 28 vdata[CS_RAW].mask = VDSO_PRECISION_MASK;
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/linux-master/include/linux/clk/ |
H A D | pxa.h | 12 extern void pxa3xx_clk_update_accr(u32 disable, u32 enable, u32 xclkcfg, u32 mask); 15 #define pxa3xx_clk_update_accr(disable, enable, xclkcfg, mask) do { } while (0)
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/linux-master/drivers/iio/gyro/ |
H A D | st_gyro_core.c | 79 .mask = 0xc0, 89 .mask = 0x08, 95 .mask = ST_SENSORS_DEFAULT_AXIS_MASK, 99 .mask = 0x30, 120 .mask = 0x80, 125 .mask = 0x08, 134 .mask = 0x07, 157 .mask = 0xc0, 167 .mask = 0x08, 173 .mask 377 st_gyro_read_raw(struct iio_dev *indio_dev, struct iio_chan_spec const *ch, int *val, int *val2, long mask) argument 406 st_gyro_write_raw(struct iio_dev *indio_dev, struct iio_chan_spec const *chan, int val, int val2, long mask) argument [all...] |
/linux-master/drivers/gpu/drm/gma500/ |
H A D | psb_irq.h | 26 void gma_enable_pipestat(struct drm_psb_private *dev_priv, int pipe, u32 mask); 27 void gma_disable_pipestat(struct drm_psb_private *dev_priv, int pipe, u32 mask);
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/linux-master/arch/csky/include/asm/ |
H A D | smp.h | 16 void arch_send_call_function_ipi_mask(struct cpumask *mask); 20 void __init set_send_ipi(void (*func)(const struct cpumask *mask), int irq);
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/linux-master/arch/sh/boards/mach-dreamcast/ |
H A D | irq.c | 46 #define EMR_BASE 0x005f6910 /* Base event mask register */ 67 __u32 mask; local 69 mask = inl(emr); 70 mask &= ~(1 << EVENT_BIT(irq)); 71 outl(mask, emr); 79 __u32 mask; local 81 mask = inl(emr); 82 mask |= (1 << EVENT_BIT(irq)); 83 outl(mask, emr);
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/linux-master/arch/csky/abiv2/ |
H A D | cacheflush.c | 42 cpumask_t *mask = &mm->context.icache_stale_mask; local 44 if (cpumask_test_cpu(cpu, mask)) { 45 cpumask_clear_cpu(cpu, mask); 59 cpumask_t others, *mask; local 72 mask = &mm->context.icache_stale_mask; 73 cpumask_setall(mask); 77 cpumask_clear_cpu(cpu, mask); 88 cpumask_clear(mask);
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/linux-master/drivers/net/wireless/realtek/rtw89/ |
H A D | debug.h | 64 void rtw89_debug(struct rtw89_dev *rtwdev, enum rtw89_debug_mask mask, 67 enum rtw89_debug_mask mask, 71 if (!(rtw89_debug_mask & mask)) 78 enum rtw89_debug_mask mask) 80 return !!(rtw89_debug_mask & mask); 84 enum rtw89_debug_mask mask, 87 enum rtw89_debug_mask mask, 91 enum rtw89_debug_mask mask) 66 rtw89_hex_dump(struct rtw89_dev *rtwdev, enum rtw89_debug_mask mask, const char *prefix_str, const void *buf, size_t len) argument 77 rtw89_debug_is_enabled(struct rtw89_dev *rtwdev, enum rtw89_debug_mask mask) argument 83 rtw89_debug(struct rtw89_dev *rtwdev, enum rtw89_debug_mask mask, const char *fmt, ...) argument 86 rtw89_hex_dump(struct rtw89_dev *rtwdev, enum rtw89_debug_mask mask, const char *prefix_str, const void *buf, size_t len) argument 90 rtw89_debug_is_enabled(struct rtw89_dev *rtwdev, enum rtw89_debug_mask mask) argument
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