Searched refs:iobase (Results 51 - 75 of 282) sorted by relevance

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/linux-master/drivers/comedi/drivers/
H A Ddas08_cs.c54 unsigned long iobase; local
64 iobase = link->resource[0]->start;
70 return das08_common_attach(dev, iobase);
H A Dadv_pci1723.c38 * PCI Bar 2 I/O Register map (dev->iobase)
88 outw(val, dev->iobase + PCI1723_AO_REG(chan));
113 outw(mode, dev->iobase + PCI1723_DIO_CTRL_REG);
124 outw(s->state, dev->iobase + PCI1723_DIO_DATA_REG);
126 data[1] = inw(dev->iobase + PCI1723_DIO_DATA_REG);
143 dev->iobase = pci_resource_start(pcidev, 2);
162 outw(PCI1723_SYNC_CTRL_SYNC, dev->iobase + PCI1723_SYNC_CTRL_REG);
166 outw(0, dev->iobase + PCI1723_RANGE_STROBE_REG);
168 outw(0x8000, dev->iobase + PCI1723_AO_REG(i));
171 outw(0, dev->iobase
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H A Drti800.c140 status = inb(dev->iobase + RTI800_CSR);
142 outb(0, dev->iobase + RTI800_CLRFLAGS);
162 inb(dev->iobase + RTI800_ADCHI);
163 outb(0, dev->iobase + RTI800_CLRFLAGS);
168 outb(devpriv->muxgain_bits, dev->iobase + RTI800_MUXGAIN);
185 outb(0, dev->iobase + RTI800_CONVERT);
191 val = inb(dev->iobase + RTI800_ADCLO);
192 val |= (inb(dev->iobase + RTI800_ADCHI) & 0xf) << 8;
222 outb(val & 0xff, dev->iobase + reg_lo);
223 outb((val >> 8) & 0xff, dev->iobase
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H A Dni_at_a2150.c148 status = inw(dev->iobase + STATUS_REG);
215 outw(0x00, dev->iobase + DMA_TC_CLEAR_REG);
228 outw(devpriv->irq_dma_bits, dev->iobase + IRQ_DMA_CNTRL_REG);
234 outw(0, dev->iobase + FIFO_RESET_REG);
478 outw(0, dev->iobase + FIFO_RESET_REG);
499 outw(devpriv->config_bits, dev->iobase + CONFIG_REG);
522 outw(0x00, dev->iobase + DMA_TC_CLEAR_REG);
526 outw(devpriv->irq_dma_bits, dev->iobase + IRQ_DMA_CNTRL_REG);
554 outw(trigger_bits, dev->iobase + TRIGGER_REG);
558 outw(0, dev->iobase
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H A Dpcmda12.c66 unsigned long ioreg = dev->iobase + (chan * 2);
98 inb(dev->iobase);
109 outb(0, dev->iobase + (i * 2));
110 outb(0, dev->iobase + (i * 2) + 1);
113 inb(dev->iobase);
H A Dadv_pci1710.c39 * PCI BAR2 Register map (dev->iobase)
272 outw(PCI171X_MUX_CHAN(chan), dev->iobase + PCI171X_MUX_REG);
273 outw(rangeval, dev->iobase + PCI171X_RANGE_REG);
283 outw(devpriv->mux_scan, dev->iobase + PCI171X_MUX_REG);
293 status = inw(dev->iobase + PCI171X_STATUS_REG);
309 sample = inw(dev->iobase + PCI171X_AD_DATA_REG);
339 outw(devpriv->ctrl, dev->iobase + PCI171X_CTRL_REG);
341 outb(0, dev->iobase + PCI171X_CLRFIFO_REG);
342 outb(0, dev->iobase + PCI171X_CLRINT_REG);
350 outw(0, dev->iobase
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H A Ddt2815.c64 status = inb(dev->iobase + DT2815_STATUS);
102 outb(lo, dev->iobase + DT2815_DATA);
108 outb(hi, dev->iobase + DT2815_DATA);
179 outb(0x00, dev->iobase + DT2815_STATUS);
185 status = inb(dev->iobase + DT2815_STATUS);
190 outb(program, dev->iobase + DT2815_DATA);
199 outb(0x00, dev->iobase + DT2815_STATUS);
H A Dadq12b.c99 status = inb(dev->iobase + ADQ12B_STINR);
120 outb(val, dev->iobase + ADQ12B_CTREG);
125 val = inb(dev->iobase + ADQ12B_ADLOW); /* trigger A/D */
132 val = inb(dev->iobase + ADQ12B_ADHIG) << 8;
133 val |= inb(dev->iobase + ADQ12B_ADLOW); /* retriggers A/D */
146 data[1] = (inb(dev->iobase + ADQ12B_STINR) & ADQ12B_STINR_IN_MASK);
166 dev->iobase + ADQ12B_OUTBR);
H A Dadv_pci1720.c48 * PCI BAR2 Register map (dev->iobase)
80 val = inb(dev->iobase + PCI1720_AO_RANGE_REG);
83 outb(val, dev->iobase + PCI1720_AO_RANGE_REG);
89 outb(val & 0xff, dev->iobase + PCI1720_AO_LSB_REG(chan));
90 outb((val >> 8) & 0xff, dev->iobase + PCI1720_AO_MSB_REG(chan));
106 data[1] = inb(dev->iobase + PCI1720_BOARDID_REG);
121 dev->iobase = pci_resource_start(pcidev, 2);
150 outb(0, dev->iobase + PCI1720_SYNC_CTRL_REG);
H A Ddas1800.c343 insw(dev->iobase + DAS1800_FIFO, devpriv->fifo_buf, nsamples);
353 while (inb(dev->iobase + DAS1800_STATUS) & FNE) {
354 dpnt = inw(dev->iobase + DAS1800_FIFO);
414 outb(CLEAR_INTR_MASK & ~DMATC, dev->iobase + DAS1800_STATUS);
430 outb(0x0, dev->iobase + DAS1800_STATUS);
431 outb(0x0, dev->iobase + DAS1800_CONTROL_B);
432 outb(0x0, dev->iobase + DAS1800_CONTROL_A);
451 unsigned int status = inb(dev->iobase + DAS1800_STATUS);
454 outb(ADC, dev->iobase + DAS1800_SELECT);
467 outb(CLEAR_INTR_MASK & ~OVF, dev->iobase
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H A Daddi_apci_2032.c48 s->state = inl(dev->iobase + APCI2032_DO_REG);
51 outl(s->state, dev->iobase + APCI2032_DO_REG);
63 data[1] = inl(dev->iobase + APCI2032_INT_STATUS_REG) & 3;
74 outl(0x0, dev->iobase + APCI2032_INT_CTRL_REG);
141 outl(enabled_isns, dev->iobase + APCI2032_INT_CTRL_REG);
174 val = inl(dev->iobase + APCI2032_STATUS_REG) & APCI2032_STATUS_IRQ;
181 val = inl(dev->iobase + APCI2032_INT_STATUS_REG) & 3;
183 outl(~val & 3, dev->iobase + APCI2032_INT_CTRL_REG);
218 outl(0x0, dev->iobase + APCI2032_DO_REG);
219 outl(0x0, dev->iobase
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H A Ds526.c179 outw((val >> 16) & 0xffff, dev->iobase + S526_GPCT_MSB_REG(chan));
180 outw(val & 0xffff, dev->iobase + S526_GPCT_LSB_REG(chan));
189 val = inw(dev->iobase + S526_GPCT_LSB_REG(chan)) & 0xffff;
190 val |= (inw(dev->iobase + S526_GPCT_MSB_REG(chan)) & 0xff) << 16;
235 outw(val, dev->iobase + S526_GPCT_MODE_REG(chan));
242 dev->iobase + S526_GPCT_CTRL_REG(chan));
246 * dev->iobase + S526_GPCT_CTRL_REG(chan));
276 outw(val, dev->iobase + S526_GPCT_MODE_REG(chan));
284 dev->iobase + S526_GPCT_CTRL_REG(chan));
291 dev->iobase
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H A Dme4000.c389 ctrl = inl(dev->iobase + ME4000_AI_CTRL_REG);
391 outl(ctrl, dev->iobase + ME4000_AI_CTRL_REG);
394 outl(0x0, dev->iobase + ME4000_AI_CTRL_REG);
415 outl(0x8000, dev->iobase + ME4000_AO_SINGLE_REG(chan));
422 outl(val, dev->iobase + ME4000_AO_CTRL_REG(chan));
426 dev->iobase + ME4000_AO_DEMUX_ADJUST_REG);
432 if (!(inl(dev->iobase + ME4000_DIO_DIR_REG) & 0x1))
433 outl(0x1, dev->iobase + ME4000_DIO_CTRL_REG);
442 val = inl(dev->iobase + ME4000_AI_DATA_REG);
453 status = inl(dev->iobase
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H A Ddt282x.c447 dev->iobase + DT2821_SUPCSR_REG);
467 dev->iobase + DT2821_SUPCSR_REG);
506 adcsr = inw(dev->iobase + DT2821_ADCSR_REG);
507 dacsr = inw(dev->iobase + DT2821_DACSR_REG);
508 supcsr = inw(dev->iobase + DT2821_SUPCSR_REG);
543 dev->iobase + DT2821_CHANCSR_REG);
551 dev->iobase + DT2821_ADCSR_REG);
553 outw(DT2821_CHANCSR_NUMB(n), dev->iobase + DT2821_CHANCSR_REG);
563 status = inw(dev->iobase + DT2821_ADCSR_REG);
597 outw(devpriv->adcsr, dev->iobase
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H A Dadv_pci1760.c101 outb(val & 0xff, dev->iobase + PCI1760_OMB_REG(0));
102 outb((val >> 8) & 0xff, dev->iobase + PCI1760_OMB_REG(1));
103 outb(cmd, dev->iobase + PCI1760_OMB_REG(2));
104 outb(0, dev->iobase + PCI1760_OMB_REG(3));
109 if (inb(dev->iobase + PCI1760_IMB_REG(2)) == cmd) {
111 return inb(dev->iobase + PCI1760_IMB_REG(0)) |
112 (inb(dev->iobase + PCI1760_IMB_REG(1)) << 8);
127 if (inb(dev->iobase + PCI1760_IMB_REG(2)) == cmd) {
153 data[1] = inb(dev->iobase + PCI1760_IMB_REG(3));
303 outb(0, dev->iobase
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H A Ddt2811.c186 val = inb(dev->iobase + DT2811_ADDATA_LO_REG) |
187 (inb(dev->iobase + DT2811_ADDATA_HI_REG) << 8);
203 status = inb(dev->iobase + DT2811_ADCSR_REG);
209 dev->iobase + DT2811_ADCSR_REG);
236 outb(DT2811_ADCSR_ADMODE(0), dev->iobase + DT2811_ADCSR_REG);
248 dev->iobase + DT2811_ADGCR_REG);
295 outb(mode | DT2811_ADCSR_INTENB, dev->iobase + DT2811_ADCSR_REG);
298 outb(devpriv->ai_divisor, dev->iobase + DT2811_TMRCTR_REG);
465 status = inb(dev->iobase + DT2811_ADCSR_REG);
505 outb(val & 0xff, dev->iobase
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H A Dcb_das16_cs.c131 status = inw(dev->iobase + DAS16CS_MISC1_REG);
150 dev->iobase + DAS16CS_AI_MUX_REG);
159 outw(devpriv->misc1, dev->iobase + DAS16CS_MISC1_REG);
176 outw(devpriv->misc2, dev->iobase + DAS16CS_MISC2_REG);
179 outw(0, dev->iobase + DAS16CS_AI_DATA_REG);
185 data[i] = inw(dev->iobase + DAS16CS_AI_DATA_REG);
206 outw(devpriv->misc1, dev->iobase + DAS16CS_MISC1_REG);
216 outw(misc1, dev->iobase + DAS16CS_MISC1_REG);
224 outw(misc1, dev->iobase + DAS16CS_MISC1_REG);
227 dev->iobase
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H A Dpcl711.c158 outb(mode, dev->iobase + PCL711_MODE_REG);
166 val = inb(dev->iobase + PCL711_AI_MSB_REG) << 8;
167 val |= inb(dev->iobase + PCL711_AI_LSB_REG);
175 outb(PCL711_INT_STAT_CLR, dev->iobase + PCL711_INT_STAT_REG);
194 outb(PCL711_INT_STAT_CLR, dev->iobase + PCL711_INT_STAT_REG);
216 outb(PCL711_AI_GAIN(range), dev->iobase + PCL711_AI_GAIN_REG);
230 outb(mux | PCL711_MUX_CHAN(chan), dev->iobase + PCL711_MUX_REG);
240 status = inb(dev->iobase + PCL711_AI_MSB_REG);
259 outb(PCL711_SOFTTRIG, dev->iobase + PCL711_SOFTTRIG_REG);
346 outb(PCL711_INT_STAT_CLR, dev->iobase
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/linux-master/drivers/dma/ioat/
H A Ddca.c90 void __iomem *iobase; member in struct:ioat_dca_priv
139 ioatdca->iobase + global_req_table + (i * 4));
164 writel(0, ioatdca->iobase + global_req_table + (i * 4));
212 static int ioat_dca_count_dca_slots(void *iobase, u16 dca_offset) argument
218 global_req_table = readw(iobase + dca_offset + IOAT3_DCA_GREQID_OFFSET);
223 req = readl(iobase + global_req_table + (slots * sizeof(u32)));
247 struct dca_provider *ioat_dca_init(struct pci_dev *pdev, void __iomem *iobase) argument
270 dca_offset = readw(iobase + IOAT_DCAOFFSET_OFFSET);
274 slots = ioat_dca_count_dca_slots(iobase, dca_offset);
284 ioatdca->iobase
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/linux-master/drivers/irqchip/
H A Dirq-dw-apb-ictl.c121 void __iomem *iobase; local
150 iobase = ioremap(r.start, resource_size(&r));
151 if (!iobase) {
165 writel_relaxed(~0, iobase + APB_INT_MASK_L);
166 writel_relaxed(~0, iobase + APB_INT_MASK_H);
167 writel_relaxed(~0, iobase + APB_INT_ENABLE_L);
168 writel_relaxed(~0, iobase + APB_INT_ENABLE_H);
170 reg = readl_relaxed(iobase + APB_INT_ENABLE_H);
174 nrirqs = fls(readl_relaxed(iobase + APB_INT_ENABLE_L));
193 gc->reg_base = iobase
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/linux-master/drivers/usb/isp1760/
H A Disp1760-if.c36 u8 __iomem *iobase; local
55 iobase = ioremap(mem_start, mem_length);
56 if (!iobase) {
80 writel(0xface, iobase + ISP176x_HC_SCRATCH);
82 reg_data = readl(iobase + ISP176x_HC_SCRATCH) & 0x0000ffff;
86 iounmap(iobase);
106 iobase = ioremap(mem_start, mem_length);
107 if (!iobase) {
115 reg_data = readl(iobase + PLX_INT_CSR_REG);
117 writel(reg_data, iobase
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/linux-master/drivers/clocksource/
H A Ddw_apb_timer_of.c87 void __iomem *iobase; local
96 ret = timer_get_base_and_rate(event_timer, &iobase, &rate);
100 ced = dw_apb_clockevent_init(-1, event_timer->name, 300, iobase, irq,
115 void __iomem *iobase; local
120 ret = timer_get_base_and_rate(source_timer, &iobase, &rate);
124 cs = dw_apb_clocksource_init(300, source_timer->name, iobase, rate);
136 sched_io_base = iobase + 0x04;
/linux-master/drivers/char/hw_random/
H A Damd-rng.c57 void __iomem *iobase; member in struct:amd768_priv
76 if (ioread32(priv->iobase + RNGDONE) == 0) {
86 *data = ioread32(priv->iobase + RNGDATA);
168 priv->iobase = ioport_map(pmbase + PMBASE_OFFSET, PMBASE_SIZE);
169 if (!priv->iobase) {
188 ioport_unmap(priv->iobase);
206 ioport_unmap(priv->iobase);
/linux-master/drivers/watchdog/
H A Dasm9260_wdt.c61 void __iomem *iobase; member in struct:asm9260_wdt_priv
71 iowrite32(0xaa, priv->iobase + HW_WDFEED);
72 iowrite32(0x55, priv->iobase + HW_WDFEED);
82 counter = ioread32(priv->iobase + HW_WDTV);
94 iowrite32(counter, priv->iobase + HW_WDTC);
107 iowrite32(BM_MOD_WDEN | mode, priv->iobase + HW_WDMOD);
139 iowrite32(BM_MOD_WDEN | BM_MOD_WDRESET, priv->iobase + HW_WDMOD);
141 iowrite32(0xff, priv->iobase + HW_WDTC);
148 iowrite32(0xff, priv->iobase + HW_WDFEED);
158 stat = ioread32(priv->iobase
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/linux-master/drivers/video/
H A Dvgastate.c34 static inline unsigned char vga_rcrtcs(void __iomem *regbase, unsigned short iobase, argument
37 vga_w(regbase, iobase + 0x4, reg);
38 return vga_r(regbase, iobase + 0x5);
41 static inline void vga_wcrtcs(void __iomem *regbase, unsigned short iobase, argument
44 vga_w(regbase, iobase + 0x4, reg);
45 vga_w(regbase, iobase + 0x5, val);
53 unsigned short iobase; local
57 iobase = (misc & 1) ? 0x3d0 : 0x3b0;
59 vga_r(state->vgabase, iobase + 0xa);
62 vga_r(state->vgabase, iobase
229 unsigned short iobase; local
260 unsigned short iobase; local
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