Searched refs:hwirq (Results 51 - 75 of 384) sorted by relevance

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/linux-master/drivers/irqchip/
H A Dirq-ixp4xx.c77 if (ixi->is_356 && d->hwirq >= 32) {
79 val &= ~BIT(d->hwirq - 32);
83 val &= ~BIT(d->hwirq);
97 if (ixi->is_356 && d->hwirq >= 32) {
99 val |= BIT(d->hwirq - 32);
103 val |= BIT(d->hwirq);
131 unsigned long *hwirq,
136 *hwirq = fwspec->param[0];
144 *hwirq = fwspec->param[0];
158 irq_hw_number_t hwirq; local
129 ixp4xx_irq_domain_translate(struct irq_domain *domain, struct irq_fwspec *fwspec, unsigned long *hwirq, unsigned int *type) argument
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H A Dirq-mvebu-gicp.c62 msg[0].data = data->hwirq;
65 msg[1].data = data->hwirq;
85 unsigned int hwirq; local
89 hwirq = find_first_zero_bit(gicp->spi_bitmap, gicp->spi_cnt);
90 if (hwirq == gicp->spi_cnt) {
94 __set_bit(hwirq, gicp->spi_bitmap);
100 fwspec.param[1] = gicp_idx_to_spi(gicp, hwirq) - 32;
113 ret = irq_domain_set_hwirq_and_chip(domain, virq, hwirq,
124 __clear_bit(hwirq, gicp->spi_bitmap);
135 if (d->hwirq >
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H A Dirq-imx-gpcv2.c76 unsigned int idx = d->hwirq / 32;
81 mask = BIT(d->hwirq % 32);
102 reg = gpcv2_idx_to_reg(cd, d->hwirq / 32);
104 val &= ~BIT(d->hwirq % 32);
118 reg = gpcv2_idx_to_reg(cd, d->hwirq / 32);
120 val |= BIT(d->hwirq % 32);
142 unsigned long *hwirq,
153 *hwirq = fwspec->param[1];
167 irq_hw_number_t hwirq; local
172 err = imx_gpcv2_domain_translate(domain, fwspec, &hwirq,
140 imx_gpcv2_domain_translate(struct irq_domain *d, struct irq_fwspec *fwspec, unsigned long *hwirq, unsigned int *type) argument
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H A Dirq-nvic.c43 irq_hw_number_t hwirq = (icsr & V7M_SCB_ICSR_VECTACTIVE) - 16; local
45 generic_handle_domain_irq(nvic_irq_domain, hwirq);
52 irq_hw_number_t hwirq; local
56 ret = irq_domain_translate_onecell(domain, fwspec, &hwirq, &type);
61 irq_map_generic_chip(domain, virq + i, hwirq + i);
H A Dirq-renesas-rzg2l.c88 static void rzg2l_clear_irq_int(struct rzg2l_irqc_priv *priv, unsigned int hwirq) argument
90 unsigned int hw_irq = hwirq - IRQC_IRQ_START;
111 static void rzg2l_clear_tint_int(struct rzg2l_irqc_priv *priv, unsigned int hwirq) argument
113 u32 bit = BIT(hwirq - IRQC_TINT_START);
178 unsigned int hwirq = irqd_to_hwirq(d); local
179 u32 iitseln = hwirq - IRQC_IRQ_START;
212 rzg2l_clear_irq_int(priv, hwirq);
237 unsigned int hwirq = irqd_to_hwirq(d); local
238 u32 titseln = hwirq - IRQC_TINT_START;
270 rzg2l_clear_tint_int(priv, hwirq);
346 irq_hw_number_t hwirq; local
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H A Dirq-aspeed-vic.c110 unsigned int sidx = d->hwirq >> 5;
111 unsigned int sbit = 1u << (d->hwirq & 0x1f);
121 unsigned int sidx = d->hwirq >> 5;
122 unsigned int sbit = 1u << (d->hwirq & 0x1f);
130 unsigned int sidx = d->hwirq >> 5;
131 unsigned int sbit = 1u << (d->hwirq & 0x1f);
140 unsigned int sidx = d->hwirq >> 5;
141 unsigned int sbit = 1u << (d->hwirq & 0x1f);
160 irq_hw_number_t hwirq)
163 unsigned int sidx = hwirq >>
159 avic_map(struct irq_domain *d, unsigned int irq, irq_hw_number_t hwirq) argument
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H A Dirq-mips-gic.c113 irq_hw_number_t hwirq = GIC_HWIRQ_TO_SHARED(irqd_to_hwirq(d)); local
115 write_gic_wedge(GIC_WEDGE_RW | hwirq);
181 unsigned int intr = GIC_HWIRQ_TO_SHARED(d->hwirq);
189 unsigned int intr = GIC_HWIRQ_TO_SHARED(d->hwirq);
201 unsigned int irq = GIC_HWIRQ_TO_SHARED(d->hwirq);
211 irq = GIC_HWIRQ_TO_SHARED(d->hwirq);
262 unsigned int irq = GIC_HWIRQ_TO_SHARED(d->hwirq);
332 int intr = GIC_HWIRQ_TO_LOCAL(d->hwirq);
339 int intr = GIC_HWIRQ_TO_LOCAL(d->hwirq);
356 intr = GIC_HWIRQ_TO_LOCAL(d->hwirq);
468 gic_irq_domain_map(struct irq_domain *d, unsigned int virq, irq_hw_number_t hwirq) argument
550 irq_hw_number_t hwirq; local
593 irq_hw_number_t hwirq, base_hwirq; local
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H A Dirq-xtensa-mx.c42 * two cell bindings. First cell value maps directly to the hwirq number.
43 * Second cell if present specifies whether hwirq number is external (1) or
72 unsigned int mask = 1u << d->hwirq;
76 unsigned int ext_irq = xtensa_get_ext_irq_no(d->hwirq);
90 unsigned int mask = 1u << d->hwirq;
94 unsigned int ext_irq = xtensa_get_ext_irq_no(d->hwirq);
118 xtensa_set_sr(1 << d->hwirq, intclear);
123 unsigned int mask = 1u << d->hwirq;
137 set_er(mask, MIROUT(d->hwirq - HW_IRQ_MX_BASE));
H A Dirq-sun6i-r.c161 unsigned long offset_from_nmi = data->hwirq - nmi_hwirq;
165 else if (test_bit(data->hwirq, wake_mux_valid))
166 assign_bit(data->hwirq, wake_mux_enabled, on);
200 unsigned long *hwirq,
205 *hwirq = nmi_hwirq;
216 *hwirq = fwspec->param[1];
228 unsigned long hwirq; local
232 ret = sun6i_r_intc_domain_translate(domain, fwspec, &hwirq, &type);
235 if (hwirq + nr_irqs > SUN6I_NR_MUX_BITS)
242 .param = { GIC_SPI, hwirq, typ
198 sun6i_r_intc_domain_translate(struct irq_domain *domain, struct irq_fwspec *fwspec, unsigned long *hwirq, unsigned int *type) argument
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H A Dirq-meson-gpio.c50 unsigned int channel, unsigned long hwirq);
54 unsigned long hwirq);
63 unsigned int channel, unsigned long hwirq);
205 unsigned int channel, unsigned long hwirq)
215 hwirq << bit_offset);
220 unsigned long hwirq)
230 hwirq << bit_offset);
241 unsigned long hwirq,
266 ctl->params->ops.gpio_irq_sel_pin(ctl, idx, hwirq);
269 * Get the hwirq numbe
204 meson8_gpio_irq_sel_pin(struct meson_gpio_irq_controller *ctl, unsigned int channel, unsigned long hwirq) argument
218 meson_a1_gpio_irq_sel_pin(struct meson_gpio_irq_controller *ctl, unsigned int channel, unsigned long hwirq) argument
240 meson_gpio_irq_request_channel(struct meson_gpio_irq_controller *ctl, unsigned long hwirq, u32 **channel_hwirq) argument
431 meson_gpio_irq_domain_translate(struct irq_domain *domain, struct irq_fwspec *fwspec, unsigned long *hwirq, unsigned int *type) argument
445 meson_gpio_irq_allocate_gic_irq(struct irq_domain *domain, unsigned int virq, u32 hwirq, unsigned int type) argument
468 unsigned long hwirq; local
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H A Dqcom-irq-combiner.c56 int hwirq; local
71 hwirq = irq_nr(reg, bit);
72 generic_handle_domain_irq(combiner->domain, hwirq);
82 struct combiner_reg *reg = combiner->regs + data->hwirq / REG_SIZE;
84 clear_bit(data->hwirq % REG_SIZE, &reg->enabled);
90 struct combiner_reg *reg = combiner->regs + data->hwirq / REG_SIZE;
92 set_bit(data->hwirq % REG_SIZE, &reg->enabled);
102 irq_hw_number_t hwirq)
116 unsigned long *hwirq, unsigned int *type)
127 *hwirq
101 combiner_irq_map(struct irq_domain *domain, unsigned int irq, irq_hw_number_t hwirq) argument
115 combiner_irq_translate(struct irq_domain *d, struct irq_fwspec *fws, unsigned long *hwirq, unsigned int *type) argument
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H A Dirq-mtk-sysirq.c28 irq_hw_number_t hwirq = data->hwirq; local
30 u8 intpol_idx = chip_data->intpol_idx[hwirq];
37 reg_index = chip_data->which_word[hwirq];
38 offset = hwirq & 0x1f;
73 unsigned long *hwirq,
84 *hwirq = fwspec->param[1];
96 irq_hw_number_t hwirq; local
107 hwirq = fwspec->param[1];
109 irq_domain_set_hwirq_and_chip(domain, virq + i, hwirq
71 mtk_sysirq_domain_translate(struct irq_domain *d, struct irq_fwspec *fwspec, unsigned long *hwirq, unsigned int *type) argument
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H A Dirq-bcm2835.c47 /* Put the bank and irq (32 bits) into the hwirq */
94 writel_relaxed(HWIRQ_BIT(d->hwirq), intc.disable[HWIRQ_BANK(d->hwirq)]);
99 writel_relaxed(HWIRQ_BIT(d->hwirq), intc.enable[HWIRQ_BANK(d->hwirq)]);
246 u32 hwirq; local
248 while ((hwirq = get_next_armctrl_hwirq()) != ~0)
249 generic_handle_domain_irq(intc.domain, hwirq);
254 u32 hwirq; local
256 while ((hwirq
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H A Dirq-starfive-jh8100-intc.c60 starfive_intc_bit_clear(irqc, STARFIVE_INTC_SRC0_MASK, BIT(d->hwirq));
69 starfive_intc_bit_set(irqc, STARFIVE_INTC_SRC0_MASK, BIT(d->hwirq));
80 irq_hw_number_t hwirq)
82 irq_domain_set_info(d, irq, hwirq, &intc_dev, d->host_data,
98 int hwirq; local
104 hwirq = ffs(value) - 1;
106 generic_handle_domain_irq(irqc->domain, hwirq);
108 starfive_intc_bit_set(irqc, STARFIVE_INTC_SRC0_CLEAR, BIT(hwirq));
109 starfive_intc_bit_clear(irqc, STARFIVE_INTC_SRC0_CLEAR, BIT(hwirq));
111 __clear_bit(hwirq,
79 starfive_intc_map(struct irq_domain *d, unsigned int irq, irq_hw_number_t hwirq) argument
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H A Dirq-loongson-pch-pic.c91 pch_pic_bitset(priv, PCH_PIC_MASK, hwirq_to_bit(priv, d->hwirq));
98 int bit = hwirq_to_bit(priv, d->hwirq);
110 int bit = hwirq_to_bit(priv, d->hwirq);
146 int bit = hwirq_to_bit(priv, d->hwirq);
168 unsigned long *hwirq,
180 *hwirq = fwspec->param[0];
186 *hwirq = fwspec->param[0] - priv->gsi_base;
195 /* Check pic-table to confirm if the hwirq has been assigned */
197 if (priv->table[i] == *hwirq) {
198 *hwirq
166 pch_pic_domain_translate(struct irq_domain *d, struct irq_fwspec *fwspec, unsigned long *hwirq, unsigned int *type) argument
222 unsigned long hwirq; local
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H A Dirq-sun4i.c179 u32 hwirq; local
182 * hwirq == 0 can mean one of 3 things:
191 hwirq = readl(irq_ic_data->irq_base + SUN4I_IRQ_VECTOR_REG) >> 2;
192 if (hwirq == 0 &&
198 generic_handle_domain_irq(irq_ic_data->irq_domain, hwirq);
199 hwirq = readl(irq_ic_data->irq_base +
201 } while (hwirq != 0);
/linux-master/drivers/pci/controller/
H A Dpci-xgene-msi.c126 static u32 hwirq_to_reg_set(unsigned long hwirq) argument
128 return (hwirq / (NR_HW_IRQS * IRQS_PER_IDX));
131 static u32 hwirq_to_group(unsigned long hwirq) argument
133 return (hwirq % NR_HW_IRQS);
136 static u32 hwirq_to_msi_data(unsigned long hwirq) argument
138 return ((hwirq / NR_HW_IRQS) % IRQS_PER_IDX);
144 u32 reg_set = hwirq_to_reg_set(data->hwirq);
145 u32 group = hwirq_to_group(data->hwirq);
150 msg->data = hwirq_to_msi_data(data->hwirq);
162 static int hwirq_to_cpu(unsigned long hwirq) argument
167 hwirq_to_canonical_hwirq(unsigned long hwirq) argument
226 u32 hwirq; local
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/linux-master/drivers/pinctrl/mediatek/
H A Dmtk-eint.c101 static int mtk_eint_flip_edge(struct mtk_eint *eint, int hwirq) argument
105 u32 mask = BIT(hwirq & 0x1f);
106 u32 port = (hwirq >> 5) & eint->hw->port_mask;
109 curr_level = eint->gpio_xlate->get_gpio_state(eint->pctl, hwirq);
120 hwirq);
129 u32 mask = BIT(d->hwirq & 0x1f);
130 void __iomem *reg = mtk_eint_get_offset(eint, d->hwirq,
133 eint->cur_mask[d->hwirq >> 5] &= ~mask;
141 u32 mask = BIT(d->hwirq & 0x1f);
142 void __iomem *reg = mtk_eint_get_offset(eint, d->hwirq,
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/linux-master/arch/arc/kernel/
H A Dmcip.c221 static void idu_irq_mask_raw(irq_hw_number_t hwirq) argument
226 __mcip_cmd_data(CMD_IDU_SET_MASK, hwirq, 1);
232 idu_irq_mask_raw(data->hwirq);
240 __mcip_cmd_data(CMD_IDU_SET_MASK, data->hwirq, 0);
249 __mcip_cmd(CMD_IDU_ACK_CIRQ, data->hwirq);
258 __mcip_cmd_data(CMD_IDU_SET_MASK, data->hwirq, 1);
259 __mcip_cmd(CMD_IDU_ACK_CIRQ, data->hwirq);
279 idu_set_dest(data->hwirq, destination_bits);
286 idu_set_mode(data->hwirq, false, 0, true, distribution_mode);
306 idu_set_mode(data->hwirq, tru
357 idu_irq_map(struct irq_domain *d, unsigned int virq, irq_hw_number_t hwirq) argument
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/linux-master/drivers/gpio/
H A Dgpio-ixp4xx.c75 __raw_writel(BIT(d->hwirq), g->base + IXP4XX_REG_GPIS);
83 gpiochip_disable_irq(gc, d->hwirq);
92 if (!(g->irq_edge & BIT(d->hwirq)))
95 gpiochip_enable_irq(gc, d->hwirq);
103 int line = d->hwirq;
113 g->irq_edge |= BIT(d->hwirq);
118 g->irq_edge |= BIT(d->hwirq);
123 g->irq_edge |= BIT(d->hwirq);
128 g->irq_edge &= ~BIT(d->hwirq);
133 g->irq_edge &= ~BIT(d->hwirq);
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H A Dgpio-xgene-sb.c57 #define HWIRQ_TO_GPIO(priv, hwirq) ((hwirq) + (priv)->irq_start)
76 int gpio = HWIRQ_TO_GPIO(priv, d->hwirq);
95 d->hwirq, lvl_type);
133 u32 gpio = HWIRQ_TO_GPIO(priv, irq_data->hwirq);
153 u32 gpio = HWIRQ_TO_GPIO(priv, irq_data->hwirq);
162 unsigned long *hwirq,
170 *hwirq = fwspec->param[0];
182 irq_hw_number_t hwirq; local
185 hwirq
160 xgene_gpio_sb_domain_translate(struct irq_domain *d, struct irq_fwspec *fwspec, unsigned long *hwirq, unsigned int *type) argument
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/linux-master/drivers/net/ethernet/wangxun/txgbe/
H A Dtxgbe_irq.c163 irq_hw_number_t hwirq)
206 int hwirq, virq; local
208 for (hwirq = 0; hwirq < txgbe->misc.nirqs; hwirq++) {
209 virq = irq_find_mapping(txgbe->misc.domain, hwirq);
227 int hwirq, err; local
235 for (hwirq = 0; hwirq < txgbe->misc.nirqs; hwirq
161 txgbe_misc_irq_domain_map(struct irq_domain *d, unsigned int irq, irq_hw_number_t hwirq) argument
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/linux-master/arch/powerpc/platforms/512x/
H A Dmpc5121_ads_cpld.c105 unsigned int hwirq; local
107 hwirq = cpld_pic_get_irq(0, PCI_IGNORE, &cpld_regs->pci_status,
109 if (hwirq != ~0) {
110 generic_handle_domain_irq(cpld_pic_host, hwirq);
114 hwirq = cpld_pic_get_irq(8, MISC_IGNORE, &cpld_regs->misc_status,
116 if (hwirq != ~0) {
117 generic_handle_domain_irq(cpld_pic_host, hwirq);
/linux-master/drivers/vfio/fsl-mc/
H A Dvfio_fsl_mc_intr.c66 int hwirq; local
69 hwirq = vdev->mc_dev->irqs[index]->virq;
71 free_irq(hwirq, irq);
81 hwirq, dev_name(&vdev->mc_dev->dev));
93 ret = request_irq(hwirq, vfio_fsl_mc_irq_handler, 0,
111 int ret, hwirq; local
139 hwirq = vdev->mc_dev->irqs[index]->virq;
/linux-master/arch/powerpc/sysdev/
H A Dfsl_msi.c8 * The hwirq alloc and free code reuse from sysdev/mpic_msi.c
72 irq_hw_number_t hwirq = irqd_to_hwirq(irqd); local
75 srs = (hwirq >> msi_data->srs_shift) & MSI_SRS_MASK;
109 int rc, hwirq; local
120 for (hwirq = 0; hwirq < NR_MSI_IRQS_MAX; hwirq++)
121 msi_bitmap_reserve_hwirq(&msi_data->bitmap, hwirq);
130 irq_hw_number_t hwirq; local
133 hwirq
142 fsl_compose_msi_msg(struct pci_dev *pdev, int hwirq, struct msi_msg *msg, struct fsl_msi *fsl_msi_data) argument
184 int rc, hwirq = -ENOMEM; local
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