Searched refs:display (Results 1 - 25 of 340) sorted by relevance

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/linux-master/drivers/misc/mei/hdcp/
H A Dmei_hdcp.h12 #include <drm/display/drm_hdcp.h>
/linux-master/drivers/gpu/drm/i915/display/
H A Dintel_dmc_wl.h25 void intel_dmc_wl_init(struct intel_display *display);
26 void intel_dmc_wl_enable(struct intel_display *display);
27 void intel_dmc_wl_disable(struct intel_display *display);
28 void intel_dmc_wl_get(struct intel_display *display, i915_reg_t reg);
29 void intel_dmc_wl_put(struct intel_display *display, i915_reg_t reg);
H A Dintel_de.h13 static inline struct intel_uncore *__to_uncore(struct intel_display *display) argument
15 return &to_i915(display->drm)->uncore;
19 __intel_de_read(struct intel_display *display, i915_reg_t reg) argument
23 intel_dmc_wl_get(display, reg);
25 val = intel_uncore_read(__to_uncore(display), reg);
27 intel_dmc_wl_put(display, reg);
34 __intel_de_read8(struct intel_display *display, i915_reg_t reg) argument
38 intel_dmc_wl_get(display, reg);
40 val = intel_uncore_read8(__to_uncore(display), reg);
42 intel_dmc_wl_put(display, re
49 __intel_de_read64_2x32(struct intel_display *display, i915_reg_t lower_reg, i915_reg_t upper_reg) argument
68 __intel_de_posting_read(struct intel_display *display, i915_reg_t reg) argument
79 __intel_de_write(struct intel_display *display, i915_reg_t reg, u32 val) argument
90 ____intel_de_rmw_nowl(struct intel_display *display, i915_reg_t reg, u32 clear, u32 set) argument
98 __intel_de_rmw(struct intel_display *display, i915_reg_t reg, u32 clear, u32 set) argument
114 ____intel_de_wait_for_register_nowl(struct intel_display *display, i915_reg_t reg, u32 mask, u32 value, unsigned int timeout) argument
124 __intel_de_wait(struct intel_display *display, i915_reg_t reg, u32 mask, u32 value, unsigned int timeout) argument
141 __intel_de_wait_fw(struct intel_display *display, i915_reg_t reg, u32 mask, u32 value, unsigned int timeout) argument
158 __intel_de_wait_custom(struct intel_display *display, i915_reg_t reg, u32 mask, u32 value, unsigned int fast_timeout_us, unsigned int slow_timeout_ms, u32 *out_value) argument
178 __intel_de_wait_for_set(struct intel_display *display, i915_reg_t reg, u32 mask, unsigned int timeout) argument
186 __intel_de_wait_for_clear(struct intel_display *display, i915_reg_t reg, u32 mask, unsigned int timeout) argument
202 __intel_de_read_fw(struct intel_display *display, i915_reg_t reg) argument
214 __intel_de_write_fw(struct intel_display *display, i915_reg_t reg, u32 val) argument
222 __intel_de_read_notrace(struct intel_display *display, i915_reg_t reg) argument
229 __intel_de_write_notrace(struct intel_display *display, i915_reg_t reg, u32 val) argument
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H A Dintel_display_conversion.h17 const struct drm_i915_private *: (&((const struct drm_i915_private *)(p))->display), \
18 struct drm_i915_private *: (&((struct drm_i915_private *)(p))->display), \
H A Dintel_dmc_wl.c16 * Wake lock is the mechanism to cause display engine to exit DC
26 * The wakelock mechanism in DMC allows the display engine to exit DC
29 * implicitly when the display engine accessed a register. With the
54 static void __intel_dmc_wl_release(struct intel_display *display) argument
56 struct drm_i915_private *i915 = to_i915(display->drm);
57 struct intel_dmc_wl *wl = &display->wl;
69 struct intel_display *display = local
79 __intel_de_rmw_nowl(display, DMC_WAKELOCK1_CTL, DMC_WAKELOCK_CTL_REQ, 0);
81 if (__intel_de_wait_for_register_nowl(display, DMC_WAKELOCK1_CTL,
110 static bool __intel_dmc_wl_supported(struct intel_display *display) argument
122 intel_dmc_wl_init(struct intel_display *display) argument
135 intel_dmc_wl_enable(struct intel_display *display) argument
162 intel_dmc_wl_disable(struct intel_display *display) argument
188 intel_dmc_wl_get(struct intel_display *display, i915_reg_t reg) argument
236 intel_dmc_wl_put(struct intel_display *display, i915_reg_t reg) argument
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H A Dintel_hti.c16 * any display resources before we create our display outputs.
19 i915->display.hti.state = intel_de_read(i915, HDPORT_STATE);
27 return i915->display.hti.state & HDPORT_ENABLED &&
28 i915->display.hti.state & HDPORT_DDI_USED(phy);
33 if (!(i915->display.hti.state & HDPORT_ENABLED))
40 return REG_FIELD_GET(HDPORT_DPLL_USED_MASK, i915->display.hti.state);
H A Dintel_quirks.c12 static void intel_set_quirk(struct intel_display *display, enum intel_quirk_id quirk) argument
14 display->quirks.mask |= BIT(quirk);
20 static void quirk_ssc_force_disable(struct intel_display *display) argument
22 intel_set_quirk(display, QUIRK_LVDS_SSC_DISABLE);
23 drm_info(display->drm, "applying lvds SSC disable quirk\n");
30 static void quirk_invert_brightness(struct intel_display *display) argument
32 intel_set_quirk(display, QUIRK_INVERT_BRIGHTNESS);
33 drm_info(display->drm, "applying inverted panel brightness quirk\n");
37 static void quirk_backlight_present(struct intel_display *display) argument
39 intel_set_quirk(display, QUIRK_BACKLIGHT_PRESEN
46 quirk_increase_t12_delay(struct intel_display *display) argument
56 quirk_increase_ddi_disabled_time(struct intel_display *display) argument
62 quirk_no_pps_backlight_power_hook(struct intel_display *display) argument
206 intel_init_quirks(struct intel_display *display) argument
227 intel_has_quirk(struct intel_display *display, enum intel_quirk_id quirk) argument
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H A Dvlv_dsi_regs.h14 #define _MIPI_MMIO_BASE(display) ((display)->dsi.mmio_base)
97 #define MIPI_DEVICE_READY(display, port) _MMIO_MIPI(_MIPI_MMIO_BASE(display), port, _MIPIA_DEVICE_READY, _MIPIC_DEVICE_READY)
107 #define MIPI_INTR_STAT(display, port) _MMIO_MIPI(_MIPI_MMIO_BASE(display), port, _MIPIA_INTR_STAT, _MIPIC_INTR_STAT)
110 #define MIPI_INTR_EN(display, port) _MMIO_MIPI(_MIPI_MMIO_BASE(display), port, _MIPIA_INTR_EN, _MIPIC_INTR_EN)
146 #define MIPI_DSI_FUNC_PRG(display, port) _MMIO_MIPI(_MIPI_MMIO_BASE(display), por
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H A Dvlv_dsi.c88 struct intel_display *display = to_intel_display(&intel_dsi->base); local
94 if (intel_de_wait_for_set(display, MIPI_GEN_FIFO_STAT(display, port),
96 drm_err(display->drm, "DPI FIFOs are not empty\n");
99 static void write_data(struct intel_display *display, argument
111 intel_de_write(display, reg, val);
115 static void read_data(struct intel_display *display, argument
122 u32 val = intel_de_read(display, reg);
134 struct intel_display *display = to_intel_display(&intel_dsi->base); local
149 data_reg = MIPI_LP_GEN_DATA(display, por
226 struct intel_display *display = to_intel_display(&intel_dsi->base); local
327 struct intel_display *display = to_intel_display(encoder); local
368 struct intel_display *display = to_intel_display(encoder); local
430 struct intel_display *display = to_intel_display(encoder); local
456 struct intel_display *display = to_intel_display(encoder); local
509 struct intel_display *display = to_intel_display(encoder); local
536 struct intel_display *display = to_intel_display(encoder); local
569 struct intel_display *display = to_intel_display(encoder); local
613 struct intel_display *display = to_intel_display(encoder); local
665 struct intel_display *display = to_intel_display(encoder); local
729 struct intel_display *display = to_intel_display(encoder); local
875 struct intel_display *display = to_intel_display(encoder); local
940 struct intel_display *display = to_intel_display(encoder); local
1016 struct intel_display *display = to_intel_display(encoder); local
1218 struct intel_display *display = to_intel_display(encoder); local
1307 struct intel_display *display = to_intel_display(encoder); local
1513 struct intel_display *display = to_intel_display(encoder); local
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H A Dintel_quirks.h22 void intel_init_quirks(struct intel_display *display);
23 bool intel_has_quirk(struct intel_display *display, enum intel_quirk_id quirk);
H A Dintel_dkl_phy.c20 spin_lock_init(&i915->display.dkl.phy_lock);
49 spin_lock(&i915->display.dkl.phy_lock);
54 spin_unlock(&i915->display.dkl.phy_lock);
70 spin_lock(&i915->display.dkl.phy_lock);
75 spin_unlock(&i915->display.dkl.phy_lock);
91 spin_lock(&i915->display.dkl.phy_lock);
96 spin_unlock(&i915->display.dkl.phy_lock);
109 spin_lock(&i915->display.dkl.phy_lock);
114 spin_unlock(&i915->display.dkl.phy_lock);
H A Dintel_frontbuffer.c51 * The other type of display power saving feature only cares about busyness
86 spin_lock(&i915->display.fb_tracking.lock);
87 frontbuffer_bits &= ~i915->display.fb_tracking.busy_bits;
88 spin_unlock(&i915->display.fb_tracking.lock);
116 spin_lock(&i915->display.fb_tracking.lock);
117 i915->display.fb_tracking.flip_bits |= frontbuffer_bits;
119 i915->display.fb_tracking.busy_bits &= ~frontbuffer_bits;
120 spin_unlock(&i915->display.fb_tracking.lock);
136 spin_lock(&i915->display.fb_tracking.lock);
138 frontbuffer_bits &= i915->display
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H A Dintel_display_reg_defs.h39 #define _MMIO_PIPE2(display, pipe, reg) _MMIO(DISPLAY_INFO(display)->pipe_offsets[(pipe)] - \
40 DISPLAY_INFO(display)->pipe_offsets[PIPE_A] + \
41 DISPLAY_MMIO_BASE(display) + (reg))
42 #define _MMIO_TRANS2(display, tran, reg) _MMIO(DISPLAY_INFO(display)->trans_offsets[(tran)] - \
43 DISPLAY_INFO(display)->trans_offsets[TRANSCODER_A] + \
44 DISPLAY_MMIO_BASE(display) + (reg))
45 #define _MMIO_CURSOR2(display, pipe, reg) _MMIO(DISPLAY_INFO(display)
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H A Dintel_wm.c47 if (i915->display.funcs.wm->update_wm)
48 i915->display.funcs.wm->update_wm(i915);
56 if (i915->display.funcs.wm->compute_pipe_wm)
57 return i915->display.funcs.wm->compute_pipe_wm(state, crtc);
67 if (!i915->display.funcs.wm->compute_intermediate_wm)
70 if (drm_WARN_ON(&i915->drm, !i915->display.funcs.wm->compute_pipe_wm))
73 return i915->display.funcs.wm->compute_intermediate_wm(state, crtc);
81 if (i915->display.funcs.wm->initial_watermarks) {
82 i915->display.funcs.wm->initial_watermarks(state, crtc);
94 if (i915->display
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H A Dintel_lpe_audio.c80 #define HAS_LPE_AUDIO(dev_priv) ((dev_priv)->display.audio.lpe.platdev != NULL)
101 rsc[0].start = rsc[0].end = dev_priv->display.audio.lpe.irq;
153 platform_device_unregister(dev_priv->display.audio.lpe.platdev);
172 int irq = dev_priv->display.audio.lpe.irq;
209 dev_priv->display.audio.lpe.irq = irq_alloc_desc(0);
210 if (dev_priv->display.audio.lpe.irq < 0) {
212 dev_priv->display.audio.lpe.irq);
213 ret = dev_priv->display.audio.lpe.irq;
217 drm_dbg(&dev_priv->drm, "irq = %d\n", dev_priv->display.audio.lpe.irq);
228 dev_priv->display
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H A Dintel_hotplug.c36 * Simply put, hotplug occurs when a display is connected to or disconnected
72 * seen when display port sink is connected, hence on platforms whose DP
75 * this is specific to DP sinks handled by this routine and any other display
127 * stored in @dev_priv->display.hotplug.hpd_storm_threshold which defaults to
133 * &dev_priv->display.hotplug.hpd_storm_threshold. However, some older systems also
148 struct intel_hotplug *hpd = &dev_priv->display.hotplug;
156 (!long_hpd && !dev_priv->display.hotplug.hpd_short_storm_enabled))
184 return i915->display.hotplug.detection_work_enabled;
238 dev_priv->display.hotplug.stats[pin].state != HPD_MARK_DISABLED)
246 dev_priv->display
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H A Dintel_dpt_common.c25 i915->display.params.enable_dpt ? 0 :
31 i915->display.params.enable_dpt ? 0 :
H A Dintel_display_driver.c5 * High level display driver entry points. This is a layer between top level
6 * driver code and low level display functionality; no low level display code or
12 #include <drm/display/drm_dp_mst_helper.h>
90 cdclk_state = to_intel_cdclk_state(i915->display.cdclk.obj.state);
93 intel_cdclk_dump_config(i915, &i915->display.cdclk.hw, "Current CDCLK");
94 cdclk_state->logical = cdclk_state->actual = i915->display.cdclk.hw;
119 INIT_LIST_HEAD(&i915->display.global.obj_list);
186 spin_lock_init(&i915->display.fb_tracking.lock);
187 mutex_init(&i915->display
207 struct intel_display *display = &i915->display; local
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/linux-master/drivers/gpu/drm/i915/
H A DMakefile35 # Support compiling the display code separately for both i915 and xe
243 display/hsw_ips.o \
244 display/i9xx_plane.o \
245 display/i9xx_wm.o \
246 display/intel_atomic.o \
247 display/intel_atomic_plane.o \
248 display/intel_audio.o \
249 display/intel_bios.o \
250 display/intel_bw.o \
251 display/intel_cdcl
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/linux-master/drivers/gpu/drm/xe/
H A DMakefile179 -I$(src)/display/ext \
181 -I$(srctree)/drivers/gpu/drm/i915/display/ \
190 # Rule to build display code shared with i915
191 $(obj)/i915-display/%.o: $(srctree)/drivers/gpu/drm/i915/display/%.c FORCE
197 display/ext/i915_irq.o \
198 display/ext/i915_utils.o \
199 display/intel_fb_bo.o \
200 display/intel_fbdev_fb.o \
201 display/xe_displa
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H A Dxe_step.c19 * lower stepping of the GT and/or display IP.
27 * Some platforms always have the same stepping value for GT and display;
39 .display = STEP_##x_
46 [0] = { COMMON_GT_MEDIA_STEP(A0), .display = STEP_B0 },
47 [1] = { COMMON_GT_MEDIA_STEP(B0), .display = STEP_D0 },
56 [0x0] = { COMMON_GT_MEDIA_STEP(A0), .display = STEP_A0 },
57 [0x1] = { COMMON_GT_MEDIA_STEP(A0), .display = STEP_A2 },
58 [0x4] = { COMMON_GT_MEDIA_STEP(B0), .display = STEP_B0 },
59 [0x8] = { COMMON_GT_MEDIA_STEP(C0), .display = STEP_B0 },
60 [0xC] = { COMMON_GT_MEDIA_STEP(D0), .display
[all...]
/linux-master/drivers/gpu/drm/xe/compat-i915-headers/
H A Dintel_step.h17 return xe_step_name(xe->info.step.display);
/linux-master/drivers/acpi/acpica/
H A Dutbuffer.c22 * display - BYTE, WORD, DWORD, or QWORD display:
27 * base_offset - Beginning buffer offset (display only)
34 void acpi_ut_dump_buffer(u8 *buffer, u32 count, u32 display, u32 base_offset) argument
40 u32 display_data_only = display & DB_DISPLAY_DATA_ONLY;
42 display &= ~DB_DISPLAY_DATA_ONLY;
49 display = DB_BYTE_DISPLAY;
69 acpi_os_printf("%*s", ((display * 2) + 1), " ");
70 j += display;
74 switch (display) {
170 acpi_ut_debug_dump_buffer(u8 *buffer, u32 count, u32 display, u32 component_id) argument
205 acpi_ut_dump_buffer_to_file(ACPI_FILE file, u8 *buffer, u32 count, u32 display, u32 base_offset) argument
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/linux-master/arch/powerpc/boot/dts/fsl/
H A Dp1022si-pre.dtsi53 vga = &display;
54 display = &display;
/linux-master/include/drm/display/
H A Ddrm_hdcp_helper.h12 #include <drm/display/drm_hdcp.h>

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