Searched refs:clock (Results 726 - 750 of 1872) sorted by relevance

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/linux-master/drivers/net/can/mscan/
H A Dmpc5xxx_can.c56 * Either the oscillator clock (SYS_XTAL_IN) or the IP bus clock
57 * (IP_CLK) can be selected as MSCAN clock source. According to
58 * the MPC5200 user's manual, the oscillator clock is the better
75 /* Determine SYS_XTAL_IN frequency from the clock domain settings */
78 dev_err(&ofdev->dev, "can't get clock node!\n");
84 dev_err(&ofdev->dev, "can't map clock node!\n");
125 /* the caller passed in the clock source spec that was read from
126 * the device tree, get the optional clock divider as well
130 of_property_read_u32(np, "fsl,mscan-clock
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/linux-master/drivers/sbus/char/
H A Dbbc_i2c.c291 writeb(bp->clock, bp->i2c_control_regs + 0x1);
343 bp->clock = readb(bp->i2c_control_regs + 0x01);
345 printk(KERN_INFO "i2c-%d: Regs at %p, %d devices, own %02x, clock %02x.\n",
346 bp->index, bp->i2c_control_regs, entry, bp->own, bp->clock);
/linux-master/fs/bcachefs/
H A Drebalance.c10 #include "clock.h"
299 struct io_clock *clock = &c->io_clock[WRITE]; local
300 u64 now = atomic64_read(&clock->now);
314 bch2_kthread_io_clock_wait(clock, r->wait_iotime_end, MAX_SCHEDULE_TIMEOUT);
/linux-master/drivers/gpu/drm/radeon/
H A Drv6xx_dpm.c139 u32 clock, struct rv6xx_sclk_stepping *step)
145 clock, false, &dividers);
154 step->vco_frequency = clock * step->post_divider;
163 u32 ref_clk = rdev->clock.spll.reference_freq;
297 u32 clock, u32 index)
301 rv6xx_convert_clock_to_stepping(rdev, clock, &step);
428 u32 ref_clk = rdev->clock.spll.reference_freq;
549 u32 clock, enum r600_power_level level)
551 u32 ref_clk = rdev->clock.spll.reference_freq;
559 if (clock
138 rv6xx_convert_clock_to_stepping(struct radeon_device *rdev, u32 clock, struct rv6xx_sclk_stepping *step) argument
296 rv6xx_generate_single_step(struct radeon_device *rdev, u32 clock, u32 index) argument
548 rv6xx_program_engine_spread_spectrum(struct radeon_device *rdev, u32 clock, enum r600_power_level level) argument
597 rv6xx_program_mclk_stepping_entry(struct radeon_device *rdev, u32 entry, u32 clock) argument
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/linux-master/drivers/gpu/drm/i915/display/
H A Dintel_backlight.c1007 * CNP: PWM clock frequency is 19.2 MHz or 24 MHz.
1019 * BXT: PWM clock frequency = 19.2 MHz.
1027 * SPT: This value represents the period of the PWM stream in clock periods
1029 * SCHICKEN_1 bit 0). PWM clock is 24 MHz.
1045 * LPT: This value represents the period of the PWM stream in clock periods
1053 u32 mul, clock; local
1061 clock = MHz(135); /* LPT:H */
1063 clock = MHz(24); /* LPT:LP */
1065 return DIV_ROUND_CLOSEST(clock, pwm_freq_hz * mul);
1082 * clock frequenc
1091 int clock; local
1109 int clock; local
1127 int mul, clock; local
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/linux-master/arch/sh/kernel/cpu/sh4a/
H A Dclock-sh7757.c3 * arch/sh/kernel/cpu/sh4/clock-sh7757.c
5 * SH7757 support for the clock framework
13 #include <asm/clock.h>
17 * Default rate for the root input clock, reset this with clk_set_rate()
67 * P clock is always enable, because some P clock modules is used
H A Dclock-shx3.c3 * arch/sh/kernel/cpu/sh4/clock-shx3.c
5 * SH-X3 support for the clock framework
15 #include <asm/clock.h>
19 * Default rate for the root input clock, reset this with clk_set_rate()
/linux-master/arch/sh/boards/mach-sdk7786/
H A Dsetup.c23 #include <asm/clock.h>
153 * Historically these include the oscillator, clock B (slots 2/3/4) and
154 * clock A (slot 1 and the CPU clock). Newer revs of the PCB shove
161 * their initial state and don't bother registering them with the clock
196 * resonator will need to provide their own input clock.
212 pr_err("FPGA clock registration failed\n");
/linux-master/arch/sh/boards/mach-se/7722/
H A Dsetup.c21 #include <asm/clock.h>
123 .id = 0, /* "keysc0" clock */
/linux-master/arch/sh/kernel/cpu/sh2a/
H A Dclock-sh7269.c3 * arch/sh/kernel/cpu/sh2a/clock-sh7269.c
5 * SH7269 clock framework support
13 #include <asm/clock.h>
25 /* Fixed 32 KHz root clock for RTC */
31 * Default rate for the root input clock, reset this with clk_set_rate()
H A Dclock-sh7264.c3 * arch/sh/kernel/cpu/sh2a/clock-sh7264.c
5 * SH7264 clock framework support
13 #include <asm/clock.h>
28 /* Fixed 32 KHz root clock for RTC */
34 * Default rate for the root input clock, reset this with clk_set_rate()
/linux-master/drivers/clk/sunxi/
H A Dclk-a10-pll2.c16 #include <dt-bindings/clock/sun4i-a10-pll2.h>
69 pr_err("Couldn't register the prediv clock\n");
102 pr_err("Couldn't register the base multiplier clock\n");
120 of_property_read_string_index(node, "clock-output-names",
132 * This clock doesn't use the post divider, and really is just
133 * a fixed divider from the PLL2 base clock.
135 of_property_read_string_index(node, "clock-output-names",
144 of_property_read_string_index(node, "clock-output-names",
153 of_property_read_string_index(node, "clock-output-names",
/linux-master/drivers/clocksource/
H A Dtimer-pxa.c19 #include <linux/sched/clock.h>
197 pr_crit("Failed to prepare clock\n");
/linux-master/drivers/net/ethernet/ti/
H A Dcpts.h106 struct ptp_clock *clock; member in struct:cpts
/linux-master/drivers/clk/renesas/
H A Dr7s9210-cpg-mssr.c15 #include <dt-bindings/clock/r7s9210-cpg-mssr.h>
112 /* The clock dividers in the table vary based on DT and register settings */
/linux-master/arch/arm/mach-omap2/
H A Dpm-debug.c21 #include <linux/sched/clock.h>
28 #include "clock.h"
/linux-master/drivers/gpu/drm/sti/
H A Dsti_hdmi_tx3g4c28phy.c78 u32 ckpxpll = hdmi->mode.clock * 1000;
96 DRM_ERROR("input TMDS clock speed (%d) not supported\n",
106 DRM_ERROR("output TMDS clock (%d) out of range\n", tmdsck);
143 * for different high speed TMDS clock frequencies a phy configuration
/linux-master/sound/firewire/tascam/
H A Dtascam.h166 enum snd_tscm_clock *clock);
/linux-master/include/drm/
H A Dgud.h67 * @clock: Pixel clock in kHz
82 __le32 clock; member in struct:gud_display_mode_req
/linux-master/drivers/net/dsa/sja1105/
H A Dsja1105_ptp.h11 /* Timestamps are in units of 8 ns clock ticks (equivalent to
12 * a fixed 125 MHz clock).
72 u64 corrclk4ts; /* use the corrected clock for timestamps */
85 struct ptp_clock *clock; member in struct:sja1105_ptp_data
87 /* Serializes all operations on the PTP hardware clock */
/linux-master/drivers/video/fbdev/aty/
H A Dmach64_ct.c46 * ATI Mach64 CT clock synthesis description.
54 * XTALIN is a fixed speed clock. Common speeds are 14.31 MHz and 29.50 MHz.
56 * FB_DIV can be set by the user for each clock individually, it should be set
57 * between 128 and 255, the chip will generate a bad clock signal for too low
59 * x depends on the type of clock; usually it is 2, but for the MCLK it can also
61 * POST_DIV can be set by the user for each clock individually, Possible values
63 * CLK is of course the clock speed that is generated.
67 * MCLK The clock rate of the chip
68 * XCLK The clock rate of the on-chip memory
69 * VCLK0 First pixel clock o
381 u8 tmp, clock; local
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/linux-master/drivers/scsi/
H A Dzorro7xx.c110 hostdata->clock = 50;
/linux-master/arch/parisc/kernel/
H A Dtime.c18 #include <linux/sched/clock.h>
51 * and increments by 1 every CPU clock tick. The architecture only
140 /* clock source code */
221 printk(KERN_ERR "Error reading tod clock\n");
/linux-master/drivers/net/can/sja1000/
H A Dtscan1.c126 priv->can.clock.freq = TSCAN1_SJA1000_XTAL / 2;
/linux-master/include/dt-bindings/clock/
H A Dr9a09g011-cpg.h8 #include <dt-bindings/clock/renesas-cpg-mssr.h>

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