Searched refs:_reg (Results 76 - 100 of 170) sorted by relevance

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/linux-master/arch/sh/kernel/cpu/sh2a/
H A Dclock-sh7269.c105 #define DIV4(_reg, _bit, _mask, _flags) \
106 SH_CLK_DIV4(&pll_clk, _reg, _bit, _mask, _flags)
H A Dclock-sh7264.c77 #define DIV4(_reg, _bit, _mask, _flags) \
78 SH_CLK_DIV4(&pll_clk, _reg, _bit, _mask, _flags)
/linux-master/drivers/clk/uniphier/
H A Dclk-uniphier.h95 #define UNIPHIER_CLK_GATE(_name, _idx, _parent, _reg, _bit) \
102 .reg = (_reg), \
/linux-master/drivers/clk/mediatek/
H A Dclk-mt8188-apmixedsys.c32 #define PLL(_id, _name, _reg, _pwr_reg, _en_mask, _flags, \
39 .reg = _reg, \
H A Dclk-mt7988-apmixed.c22 #define PLL(_id, _name, _reg, _pwr_reg, _en_mask, _flags, _rst_bar_mask, _pcwbits, _pd_reg, \
28 .reg = _reg, \
H A Dclk-mt8135-apmixedsys.c20 #define PLL(_id, _name, _reg, _pwr_reg, _en_mask, _flags, _pcwbits, _pd_reg, _pd_shift, _tuner_reg, _pcw_reg, _pcw_shift) { \
23 .reg = _reg, \
H A Dclk-mt7629.c23 #define PLL_B(_id, _name, _reg, _pwr_reg, _en_mask, _flags, _pcwbits, \
28 .reg = _reg, \
44 #define PLL(_id, _name, _reg, _pwr_reg, _en_mask, _flags, _pcwbits, \
47 PLL_B(_id, _name, _reg, _pwr_reg, _en_mask, _flags, _pcwbits, \
H A Dclk-mt8186-apmixedsys.c19 #define PLL(_id, _name, _reg, _pwr_reg, _en_mask, _flags, \
25 .reg = _reg, \
H A Dclk-mt6795-apmixedsys.c26 #define PLL(_id, _name, _reg, _pwr_reg, _en_mask, _flags, _pcwbits, \
30 .reg = _reg, \
H A Dclk-mt8195-apmixedsys.c33 #define PLL(_id, _name, _reg, _pwr_reg, _en_mask, _flags, \
40 .reg = _reg, \
/linux-master/arch/sh/kernel/cpu/sh4a/
H A Dclock-sh7343.c105 #define DIV4(_reg, _bit, _mask, _flags) \
106 SH_CLK_DIV4(&pll_clk, _reg, _bit, _mask, _flags)
125 #define MSTP(_parent, _reg, _bit, _flags) \
126 SH_CLK_MSTP32(_parent, _reg, _bit, _flags)
H A Dclock-sh7366.c108 #define DIV4(_reg, _bit, _mask, _flags) \
109 SH_CLK_DIV4(&pll_clk, _reg, _bit, _mask, _flags)
128 #define MSTP(_parent, _reg, _bit, _flags) \
129 SH_CLK_MSTP32(_parent, _reg, _bit, _flags)
H A Dclock-sh7722.c108 #define DIV4(_reg, _bit, _mask, _flags) \
109 SH_CLK_DIV4(&pll_clk, _reg, _bit, _mask, _flags)
/linux-master/sound/soc/sh/rcar/
H A Ddma.c563 #define RDMA_SSI_I_N(addr, i) (addr ##_reg - 0x00300000 + (0x40 * i) + 0x8)
564 #define RDMA_SSI_O_N(addr, i) (addr ##_reg - 0x00300000 + (0x40 * i) + 0xc)
566 #define RDMA_SSIU_I_N(addr, i, j) (addr ##_reg - 0x00441000 + (0x1000 * (i)) + (((j) / 4) * 0xA000) + (((j) % 4) * 0x400) - (0x4000 * ((i) / 9) * ((j) / 4)))
569 #define RDMA_SSIU_I_P(addr, i, j) (addr ##_reg - 0x00141000 + (0x1000 * (i)) + (((j) / 4) * 0xA000) + (((j) % 4) * 0x400) - (0x4000 * ((i) / 9) * ((j) / 4)))
572 #define RDMA_SRC_I_N(addr, i) (addr ##_reg - 0x00500000 + (0x400 * i))
573 #define RDMA_SRC_O_N(addr, i) (addr ##_reg - 0x004fc000 + (0x400 * i))
575 #define RDMA_SRC_I_P(addr, i) (addr ##_reg - 0x00200000 + (0x400 * i))
576 #define RDMA_SRC_O_P(addr, i) (addr ##_reg - 0x001fc000 + (0x400 * i))
578 #define RDMA_CMD_O_N(addr, i) (addr ##_reg - 0x004f8000 + (0x400 * i))
579 #define RDMA_CMD_O_P(addr, i) (addr ##_reg
[all...]
/linux-master/drivers/gpu/drm/i915/
H A Di915_cmd_parser.c581 #define REG32(_reg, ...) \
582 { .addr = (_reg), __VA_ARGS__ }
584 #define REG32_IDX(_reg, idx) \
585 { .addr = _reg(idx) }
594 #define REG64(_reg) \
595 { .addr = _reg }, \
596 { .addr = _reg ## _UDW }
598 #define REG64_IDX(_reg, idx) \
599 { .addr = _reg(idx) }, \
600 { .addr = _reg ## _UD
[all...]
/linux-master/drivers/regulator/
H A Dmc13783-regulator.c243 #define MC13783_DEFINE_SW(_name, _node, _reg, _vsel_reg, _voltages) \
244 MC13783_DEFINE(REG, _name, _node, _reg, _vsel_reg, _voltages)
245 #define MC13783_DEFINE_REGU(_name, _node, _reg, _vsel_reg, _voltages) \
246 MC13783_DEFINE(REG, _name, _node, _reg, _vsel_reg, _voltages)
H A Dpcap-regulator.c99 #define VREG_INFO(_vreg, _reg, _en, _index, _stby, _lowpwr) \
101 .reg = _reg, \
/linux-master/drivers/reset/
H A Dreset-uniphier.c27 #define UNIPHIER_RESET(_id, _reg, _bit) \
30 .reg = (_reg), \
34 #define UNIPHIER_RESETX(_id, _reg, _bit) \
37 .reg = (_reg), \
/linux-master/drivers/clk/mvebu/
H A Darmada-37xx-periph.c159 #define PERIPH_DIV(_name, _reg, _shift, _table) \
161 .reg = (void *)_reg, \
169 #define PERIPH_PM_CPU(_name, _shift1, _reg, _shift2) \
174 .reg_div = (void *)_reg, \
186 #define PERIPH_CLK_FULL(_name, _bit, _shift, _reg, _shift1, _table) \
189 static PERIPH_DIV(_name, _reg, _shift1, _table);
191 #define PERIPH_CLK_GATE_DIV(_name, _bit, _reg, _shift, _table) \
193 static PERIPH_DIV(_name, _reg, _shift, _table);
/linux-master/drivers/power/supply/
H A Dacer_a500_battery.c29 #define EC_DATA(_reg, _psp) { \
31 .reg = _reg, \
/linux-master/drivers/gpu/drm/imagination/
H A Dpvr_fw.h404 pvr_cr_read32((pvr_dev), (pvr_dev)->fw_dev.defs->irq.name ## _reg)
407 pvr_cr_write32((pvr_dev), (pvr_dev)->fw_dev.defs->irq.name ## _reg, value)
/linux-master/drivers/irqchip/
H A Dirq-madera.c22 #define MADERA_IRQ(_irq, _reg) \
24 .reg_offset = (_reg) - MADERA_IRQ1_STATUS_2, \
/linux-master/drivers/mfd/
H A Drc5t583.c30 #define DEEPSLEEP_INIT(_id, _reg, _pos) \
32 .reg_add = RC5T583_##_reg, \
/linux-master/include/linux/
H A Dregmap.h95 #define REG_SEQ(_reg, _def, _delay_us) { \
96 .reg = _reg, \
100 #define REG_SEQ0(_reg, _def) REG_SEQ(_reg, _def, 0)
1348 #define REG_FIELD(_reg, _lsb, _msb) { \
1349 .reg = _reg, \
1354 #define REG_FIELD_ID(_reg, _lsb, _msb, _size, _offset) { \
1355 .reg = _reg, \
/linux-master/drivers/usb/typec/tipd/
H A Dtps6598x.h15 #define TPS_FIELD_GET(_mask, _reg) ((typeof(_mask))(((_reg) & (_mask)) >> __bf_shf(_mask)))

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