Searched refs:regs (Results 51 - 75 of 223) sorted by relevance

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/haiku-fatelf/src/add-ons/accelerants/radeon/
H A Dcrtc.c22 vuint8 *regs = ai->regs; local
27 OUTREGP( regs, RADEON_CRTC_GEN_CNTL, values->crtc_gen_cntl,
30 OUTREG( regs, RADEON_CRTC_H_TOTAL_DISP, values->crtc_h_total_disp );
31 OUTREG( regs, RADEON_CRTC_H_SYNC_STRT_WID, values->crtc_h_sync_strt_wid );
32 OUTREG( regs, RADEON_CRTC_V_TOTAL_DISP, values->crtc_v_total_disp );
33 OUTREG( regs, RADEON_CRTC_V_SYNC_STRT_WID, values->crtc_v_sync_strt_wid );
34 OUTREG( regs, RADEON_CRTC_OFFSET_CNTL, values->crtc_offset_cntl );
35 OUTREG( regs, RADEON_CRTC_PITCH, values->crtc_pitch );
38 OUTREGP( regs, RADEON_CRTC2_GEN_CNT
[all...]
H A DAcceleration.c73 OUTREG(ai->regs, RADEON_DP_GUI_MASTER_CNTL, (vc->datatype << RADEON_GMC_DST_DATATYPE_SHIFT
92 OUTREG(ai->regs, RADEON_DP_CNTL, ((xdir >= 0 ? RADEON_DST_X_LEFT_TO_RIGHT : 0)
96 OUTREG( ai->regs, RADEON_SRC_Y_X, (list->src_top << 16 ) | list->src_left);
97 OUTREG( ai->regs, RADEON_DST_Y_X, (list->dest_top << 16 ) | list->dest_left);
100 OUTREG( ai->regs, RADEON_DST_HEIGHT_WIDTH, ((list->height + 1) << 16 ) | (list->width + 1));
166 OUTREG(ai->regs, RADEON_DP_GUI_MASTER_CNTL, ((vc->datatype << RADEON_GMC_DST_DATATYPE_SHIFT)
171 OUTREG(ai->regs, RADEON_DP_BRUSH_FRGD_CLR, colorIndex);
172 OUTREG(ai->regs, RADEON_DP_CNTL, (RADEON_DST_X_LEFT_TO_RIGHT | RADEON_DST_Y_TOP_TO_BOTTOM));
178 OUTREG(ai->regs, RADEON_DST_Y_X, (list->top << 16) | list->left);
179 OUTREG(ai->regs, RADEON_DST_WIDTH_HEIGH
[all...]
H A Doverlay.c56 vuint8 *regs = ai->regs; local
68 OUTREG( regs, RADEON_OV0_SCALE_CNTL, RADEON_SCALER_SOFT_RESET );
69 OUTREG( regs, RADEON_OV0_AUTO_FLIP_CNTRL, si->overlay_mgr.auto_flip_reg );
70 OUTREG( regs, RADEON_OV0_FILTER_CNTL, // use fixed filter coefficients
75 OUTREG( regs, RADEON_OV0_KEY_CNTL, RADEON_GRAPHIC_KEY_FN_EQ |
78 OUTREG( regs, RADEON_OV0_TEST, 0 );
79 // OUTREG( regs, RADEON_FCP_CNTL, RADEON_FCP_CNTL_GND ); // disable capture clock
80 // OUTREG( regs, RADEON_CAP0_TRIG_CNTL, 0 ); // disable capturing
81 OUTREG( regs, RADEON_OV0_REG_LOAD_CNT
162 vuint8 *regs = ai->regs; local
317 vuint8 *regs = ai->regs; local
535 vuint8 *regs = ai->regs; local
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H A Dmonitor_routing.c25 // read regs needed for display device routing
29 vuint8 *regs = ai->regs; local
31 values->dac_cntl = INREG( regs, RADEON_DAC_CNTL );
32 values->dac_cntl2 = INREG( regs, RADEON_DAC_CNTL2 );
33 values->crtc_ext_cntl = INREG( regs, RADEON_CRTC_EXT_CNTL );
34 values->crtc2_gen_cntl = INREG( regs, RADEON_CRTC2_GEN_CNTL );
35 values->disp_output_cntl = INREG( regs, RADEON_DISP_OUTPUT_CNTL );
36 values->pixclks_cntl = Radeon_INPLL( ai->regs, ai->si->asic, RADEON_PIXCLKS_CNTL );
37 values->vclk_ecp_cntl = Radeon_INPLL( ai->regs, a
422 vuint8 *regs = ai->regs; local
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H A DCursor.c25 OUTREG( ai->regs, RADEON_CUR_CLR0, 0xffffff );
26 OUTREG( ai->regs, RADEON_CUR_CLR1, 0 );
28 OUTREG( ai->regs, RADEON_CUR2_CLR0, 0xffffff );
29 OUTREG( ai->regs, RADEON_CUR2_CLR1, 0 );
197 OUTREG( ai->regs, RADEON_CUR_HORZ_VERT_OFF, RADEON_CUR_LOCK
200 OUTREG( ai->regs, RADEON_CUR_HORZ_VERT_POSN, RADEON_CUR_LOCK
203 OUTREG( ai->regs, RADEON_CUR_OFFSET,
206 OUTREG( ai->regs, RADEON_CUR2_HORZ_VERT_OFF, RADEON_CUR2_LOCK
209 OUTREG( ai->regs, RADEON_CUR2_HORZ_VERT_POSN, RADEON_CUR2_LOCK
212 OUTREG( ai->regs, RADEON_CUR2_OFFSE
[all...]
H A Dpalette.c41 OUTREG( ai->regs, RADEON_DAC_CNTL2,
45 OUTREG( ai->regs, RADEON_PALETTE_INDEX, 0 );
48 OUTREG( ai->regs, RADEON_PALETTE_DATA, (i << 16) | (i << 8) | i );
104 OUTREG( ai->regs, RADEON_DAC_CNTL2,
108 OUTREG( ai->regs, RADEON_PALETTE_INDEX, first );
111 OUTREG( ai->regs, RADEON_PALETTE_DATA,
H A DSetDisplayMode.c86 vuint8 *regs = ai->regs; local
90 OUTREG( regs, common_regs[i].reg, common_regs[i].val );
93 OUTREGP( regs, RADEON_CRTC_GEN_CNTL,
100 OUTREG( regs, RADEON_CRTC_MORE_CNTL, 0 );
111 vuint8 *regs = ai->regs; local
263 OUTREG( regs, RADEON_SURFACE_CNTL, surface_cntl );
283 SHOW_FLOW( 0, "RADEON_DAC_CNTL %08X ", INREG( regs, RADEON_DAC_CNTL ));
284 SHOW_FLOW( 0, "RADEON_DAC_CNTL2 %08X ", INREG( regs, RADEON_DAC_CNTL
[all...]
H A Dpll.c29 if( (Radeon_INPLL( ai->regs, ai->si->asic, crtc_idx == 0 ? RADEON_PPLL_REF_DIV : RADEON_P2PLL_REF_DIV )
40 Radeon_OUTPLLP( ai->regs, ai->si->asic,
457 vuint8 *regs = ai->regs; local
464 Radeon_OUTPLLP( regs, asic, crtc_idx == 0 ? RADEON_VCLK_ECP_CNTL : RADEON_PIXCLKS_CNTL,
467 Radeon_OUTPLLP( regs, asic,
477 OUTREGP( regs, RADEON_CLOCK_CNTL_INDEX,
481 RADEONPllErrataAfterIndex(regs, asic);
487 Radeon_OUTPLLP( regs, asic,
492 Radeon_OUTPLLP( regs, asi
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/haiku-fatelf/src/bin/gdb/gdb/
H A Dppcnbsd-tdep.c53 ppcnbsd_supply_reg (char *regs, int regno) argument
62 regs + REG_FIXREG_OFFSET (i));
67 regs + REG_LR_OFFSET);
71 regs + REG_CR_OFFSET);
75 regs + REG_XER_OFFSET);
79 regs + REG_CTR_OFFSET);
83 regs + REG_PC_OFFSET);
87 ppcnbsd_fill_reg (char *regs, int regno) argument
96 regs + REG_FIXREG_OFFSET (i));
101 regs
183 char *regs, *fpregs; local
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H A Dm32r-linux-nat.c110 elf_gregset_t regs;
112 if (ptrace (PTRACE_GETREGS, tid, 0, (int) &regs) < 0)
115 supply_gregset (&regs);
158 elf_gregset_t regs;
160 if (ptrace (PTRACE_GETREGS, tid, 0, (int) &regs) < 0)
163 fill_gregset (&regs, regno);
165 if (ptrace (PTRACE_SETREGS, tid, 0, (int) &regs) < 0)
108 elf_gregset_t regs; local
156 elf_gregset_t regs; local
H A Darm-linux-nat.c403 elf_gregset_t regs; local
408 ret = ptrace (PTRACE_GETREGS, tid, 0, &regs);
416 regcache_raw_supply (current_regcache, regno, (char *) &regs[regno]);
422 (char *) &regs[ARM_CPSR_REGNUM]);
425 (char *) &regs[ARM_PC_REGNUM]);
430 regs[ARM_PC_REGNUM] = ADDR_BITS_REMOVE (regs[ARM_PC_REGNUM]);
432 (char *) &regs[ARM_PC_REGNUM]);
443 elf_gregset_t regs; local
448 ret = ptrace (PTRACE_GETREGS, tid, 0, &regs);
477 elf_gregset_t regs; local
508 elf_gregset_t regs; local
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H A Dm68kbsd-tdep.c60 const char *regs = fpregs; local
68 regcache_raw_supply (regcache, i, regs + m68kbsd_fpreg_offset (i));
81 const char *regs = gregs; local
89 regcache_raw_supply (regcache, i, regs + i * 4);
94 regs += M68KBSD_SIZEOF_GREGS;
96 m68kbsd_supply_fpregset (regset, regcache, regnum, regs, len);
H A Dsparc-nat.c45 `struct regs' and `struct fp_status' in <machine/reg.h>. BSD's
50 and a `fpregset_t' that are equivalent to `struct regs' and `struct
61 typedef struct regs gregset_t;
168 gregset_t regs; local
170 if (ptrace (PTRACE_GETREGS, pid, (PTRACE_TYPE_ARG3) &regs, 0) == -1)
173 sparc_supply_gregset (sparc_gregset, regcache, -1, &regs);
203 gregset_t regs; local
205 if (ptrace (PTRACE_GETREGS, pid, (PTRACE_TYPE_ARG3) &regs, 0) == -1)
208 sparc_collect_gregset (sparc_gregset, regcache, regnum, &regs);
210 if (ptrace (PTRACE_SETREGS, pid, (PTRACE_TYPE_ARG3) &regs,
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H A Di387-tdep.c391 const char *regs = fsave;
418 memcpy (val, FSAVE_ADDR (regs, i), 2);
425 regcache_raw_supply (regcache, i, FSAVE_ADDR (regs, i));
453 char *regs = fsave;
479 buf[1] |= ((FSAVE_ADDR (regs, i))[1] & ~((1 << 3) - 1));
481 memcpy (FSAVE_ADDR (regs, i), buf, 2);
484 regcache_raw_collect (regcache, i, FSAVE_ADDR (regs, i));
564 const char *regs = fxsave;
579 if (regs == NULL)
592 memcpy (val, FXSAVE_ADDR (regs,
388 const char *regs = fsave; local
450 char *regs = fsave; local
559 const char *regs = fxsave; local
649 char *regs = fxsave; local
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H A Di386bsd-nat.c97 const char *regs = gregs;
105 regcache_raw_supply (regcache, regnum, regs + offset);
117 char *regs = gregs;
127 regcache_raw_collect (regcache, i, regs + offset);
140 struct reg regs;
143 (PTRACE_TYPE_ARG3) &regs, 0) == -1)
146 i386bsd_supply_gregset (current_regcache, &regs);
190 struct reg regs;
193 (PTRACE_TYPE_ARG3) &regs, 0) == -1)
196 i386bsd_collect_gregset (current_regcache, &regs, regnu
95 const char *regs = gregs; local
115 char *regs = gregs; local
138 struct reg regs; local
188 struct reg regs; local
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H A Damd64-linux-nat.c165 elf_gregset_t regs;
167 if (ptrace (PTRACE_GETREGS, tid, 0, (long) &regs) < 0)
170 amd64_supply_native_gregset (current_regcache, &regs, -1);
202 elf_gregset_t regs;
204 if (ptrace (PTRACE_GETREGS, tid, 0, (long) &regs) < 0)
207 amd64_collect_native_gregset (current_regcache, &regs, regnum);
209 if (ptrace (PTRACE_SETREGS, tid, 0, (long) &regs) < 0)
162 elf_gregset_t regs; local
199 elf_gregset_t regs; local
/haiku-fatelf/src/system/boot/platform/bios_ia32/
H A Ddevices.cpp175 struct bios_regs regs; local
176 regs.eax = BIOS_BOOT_CD_GET_STATUS;
177 regs.edx = 0;
178 regs.esi = kDataSegmentScratch;
179 call_bios(0x13, &regs);
181 if ((regs.flags & CARRY_FLAG) != 0)
205 struct bios_regs regs; local
206 regs.eax = BIOS_IS_EXT_PRESENT;
207 regs.ebx = 0x55aa;
208 regs
226 struct bios_regs regs; local
245 struct bios_regs regs; local
273 struct bios_regs regs; local
626 struct bios_regs regs; local
655 struct bios_regs regs; local
754 struct bios_regs regs; local
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/haiku-fatelf/src/add-ons/accelerants/neomagic/engine/
H A Dnm_globals.c15 vuint32 *regs, *regs2; variable
/haiku-fatelf/src/add-ons/accelerants/nvidia/engine/
H A Dnv_globals.c16 vuint32 *regs; variable
/haiku-fatelf/src/add-ons/accelerants/nvidia_gpgpu/engine/
H A Dnv_globals.c16 vuint32 *regs; variable
/haiku-fatelf/src/bin/keymap/
H A DKeymap.cpp362 struct re_registers regs; local
364 if (re_search(&versionBuf, buffer, length, 0, length, &regs) >= 0) {
365 sscanf(buffer + regs.start[1], "%" B_SCNu32, &fKeys.version);
366 } else if (re_search(&capslockBuf, buffer, length, 0, length, &regs)
368 sscanf(buffer + regs.start[1], "0x%" B_SCNx32, &fKeys.caps_key);
369 } else if (re_search(&scrolllockBuf, buffer, length, 0, length, &regs)
371 sscanf(buffer + regs.start[1], "0x%" B_SCNx32, &fKeys.scroll_key);
372 } else if (re_search(&numlockBuf, buffer, length, 0, length, &regs)
374 sscanf(buffer + regs.start[1], "0x%" B_SCNx32, &fKeys.num_key);
375 } else if (re_search(&lshiftBuf, buffer, length, 0, length, &regs)
1049 _ComputeChars(const char* buffer, struct re_registers& regs, int i, int& offset) argument
1077 _ComputeTables(const char* buffer, struct re_registers& regs, uint32& table) argument
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H A DKeymap.h53 struct re_registers& regs, int i,
56 struct re_registers& regs, uint32& table);
/haiku-fatelf/src/add-ons/kernel/drivers/graphics/radeon/
H A Dirq.c21 OUTREG(di->regs, RADEON_GEN_INT_CNTL, 0);
30 Radeon_ThreadInterruptWork(vuint8 *regs, device_info *di, uint32 int_status) argument
71 Radeon_HandleCaptureInterrupt(vuint8 *regs, device_info *di, uint32 cap_status) argument
93 OUTREG(regs, RADEON_CAP_INT_STATUS, cap_status);
106 vuint8 *regs = di->regs; local
110 full_int_status = INREG(regs, RADEON_GEN_INT_STATUS);
111 int_status = full_int_status & INREG(regs, RADEON_GEN_INT_CNTL);
116 handled = Radeon_ThreadInterruptWork(regs, di, int_status);
119 OUTREG(regs, RADEON_GEN_INT_STATU
154 vuint8 *regs = di->regs; local
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/haiku-fatelf/src/add-ons/kernel/drivers/power/x86_cpuidle/
H A Dintel_cpuidle.cpp99 if ((cpuid.regs.ecx & 0x1) == 0 ||
100 (cpuid.regs.ecx & 0x2) == 0 ||
101 cpuid.regs.edx == 0) {
107 int32 subStates = (cpuid.regs.edx >> ((i) * 4)) & 0xf;
/haiku-fatelf/src/bin/
H A Dsysinfo.cpp152 if ((info->regs.eax & 0x80000000) == 0) {
160 if ((info->regs.ebx & 0x80000000) == 0) {
169 if ((info->regs.edx & 0x80000000) == 0) {
178 if ((info->regs.ecx & 0x80000000) == 0) {
289 if (info.regs.eax)
290 print_TLB(info.regs.eax, info.regs.ebx ? "2M/4M-byte" : NULL);
291 if (info.regs.ebx)
292 print_TLB(info.regs.ebx, info.regs
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