Searched refs:SIMD (Results 26 - 33 of 33) sorted by relevance

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/haiku-buildtools/binutils/gas/testsuite/gas/i386/
H A Dx86-64-simd-intel.d4 #name: x86-64 SIMD (Intel mode)
H A Dx86-64-simd-suffix.d4 #name: x86-64 SIMD (with suffixes)
H A Dx86-64-simd.d3 #name: x86-64 SIMD
H A Dsimd-intel.d4 #name: i386 SIMD (Intel mode)
H A Dx86-64-opcode.s104 # SIMD/SSE
/haiku-buildtools/legacy/binutils/gas/testsuite/gas/i386/
H A Dx86-64-opcode.s101 # SIMD/SSE
/haiku-buildtools/binutils/opcodes/
H A Dnds32-asm.c322 /* seg-SIMD. */
323 {"pbsad", "%rt,%ra,%rb", SIMD (PBSAD), 4, ATTR (PERF2_EXT), 0, NULL, 0, NULL},
324 {"pbsada", "%rt,%ra,%rb", SIMD (PBSADA), 4, ATTR (PERF2_EXT), 0, NULL, 0, NULL},
H A Daarch64-tbl.h2028 #define SIMD &aarch64_feature_simd
2050 { NAME, OPCODE, MASK, CLASS, OP, SIMD, OPS, QUALS, FLAGS, 0, NULL }
4189 Y(SISD_REG, regno, "Sd", 0, F(FLD_Rd), "a SIMD scalar register") \
4190 Y(SISD_REG, regno, "Sn", 0, F(FLD_Rn), "a SIMD scalar register") \
4191 Y(SISD_REG, regno, "Sm", 0, F(FLD_Rm), "a SIMD scalar register") \
4192 Y(SIMD_REG, regno, "Vd", 0, F(FLD_Rd), "a SIMD vector register") \
4193 Y(SIMD_REG, regno, "Vn", 0, F(FLD_Rn), "a SIMD vector register") \
4194 Y(SIMD_REG, regno, "Vm", 0, F(FLD_Rm), "a SIMD vector register") \
4196 "the top half of a 128-bit FP/SIMD register") \
4198 "the top half of a 128-bit FP/SIMD registe
2027 #define SIMD macro
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