Searched refs:MCInstrDesc (Results 76 - 100 of 206) sorted by relevance

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/freebsd-current/contrib/llvm-project/llvm/lib/Target/ARM/
H A DARMBaseInstrInfo.cpp53 #include "llvm/MC/MCInstrDesc.h"
207 const MCInstrDesc &MCID = MI.getDesc();
620 const MCInstrDesc &MCID = MI.getDesc();
672 const MCInstrDesc &MCID = MI.getDesc();
783 const MCInstrDesc &MCID = MI.getDesc();
2370 const MCInstrDesc &DefDesc = DefMI->getDesc();
2634 const MCInstrDesc &Desc = MI.getDesc();
3326 const MCInstrDesc &DefMCID = DefMI.getDesc();
3336 const MCInstrDesc &UseMCID = UseMI.getDesc();
3464 const MCInstrDesc
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H A DARMLowOverheadLoops.cpp71 #include "llvm/MC/MCInstrDesc.h"
107 const MCInstrDesc &MCID = MI.getDesc();
824 const MCInstrDesc &MCID = MI.getDesc();
833 const MCInstrDesc &MCID = MI.getDesc();
839 const MCInstrDesc &MCID = MI.getDesc();
1243 const MCInstrDesc &MCID = MI->getDesc();
/freebsd-current/contrib/llvm-project/llvm/lib/Target/X86/MCTargetDesc/
H A DX86MCCodeEmitter.cpp22 #include "llvm/MC/MCInstrDesc.h"
483 const MCInstrDesc &Desc = MCII.get(Opcode);
955 const MCInstrDesc &Desc = MCII.get(MI.getOpcode());
1302 const MCInstrDesc &Desc = MCII.get(MI.getOpcode());
1425 const MCInstrDesc &Desc = MCII.get(MI.getOpcode());
1487 const MCInstrDesc &Desc = MCII.get(Opcode);
1504 const MCInstrDesc &Desc = MCII.get(Opcode);
/freebsd-current/contrib/llvm-project/llvm/lib/Target/AMDGPU/
H A DSIInstrInfo.h308 const MCInstrDesc &getIndirectRegWriteMovRelPseudo(unsigned VecSize,
312 const MCInstrDesc &getIndirectGPRIDXPseudo(unsigned VecSize,
325 bool findCommutedOpIndices(const MCInstrDesc &Desc, unsigned &SrcOpIdx0,
1220 const MCInstrDesc &getMCOpcodeFromPseudo(unsigned Opcode) const {
1303 const MCInstrDesc &getKillTerminatorFromPseudo(unsigned Opcode) const;
1336 const TargetRegisterClass *getRegClass(const MCInstrDesc &TID, unsigned OpNum,
H A DSIFoldOperands.cpp627 const MCInstrDesc &InstDesc = MI->getDesc();
690 const MCInstrDesc &Desc = UseMI->getDesc();
1026 const MCInstrDesc &UseDesc = UseMI->getDesc();
1060 const MCInstrDesc &FoldDesc = OpToFold.getParent()->getDesc();
1157 static void mutateCopyOp(MachineInstr &MI, const MCInstrDesc &NewDesc) {
1163 const MCInstrDesc &Desc = MI.getDesc();
1772 const MCInstrDesc &InstDesc = UseMI->getDesc();
/freebsd-current/contrib/llvm-project/llvm/lib/CodeGen/SelectionDAG/
H A DResourcePriorityQueue.cpp435 const MCInstrDesc &TID = TII->get(N->getMachineOpcode());
537 const MCInstrDesc &TID = TII->get(N->getMachineOpcode());
H A DScheduleDAGFast.cpp250 const MCInstrDesc &MCID = TII->get(N->getMachineOpcode());
424 const MCInstrDesc &MCID = TII->get(N->getMachineOpcode());
524 const MCInstrDesc &MCID = TII->get(Node->getMachineOpcode());
/freebsd-current/contrib/llvm-project/llvm/lib/Target/AArch64/
H A DAArch64ConditionalCompares.cpp630 const MCInstrDesc &MCID = TII->get(Opc);
687 const MCInstrDesc &MCID = TII->get(Opc);
/freebsd-current/contrib/llvm-project/llvm/lib/Target/AVR/
H A DAVRInstrInfo.cpp195 const MCInstrDesc &AVRInstrInfo::getBrCond(AVRCC::CondCodes CC) const {
485 const MCInstrDesc &Desc = get(Opcode);
/freebsd-current/contrib/llvm-project/llvm/lib/Target/RISCV/MCTargetDesc/
H A DRISCVMCCodeEmitter.cpp300 const MCInstrDesc &Desc = MCII.get(MI.getOpcode());
390 MCInstrDesc const &Desc = MCII.get(MI.getOpcode());
/freebsd-current/contrib/llvm-project/llvm/lib/CodeGen/
H A DMachineInstr.cpp47 #include "llvm/MC/MCInstrDesc.h"
96 /// the MCInstrDesc.
97 MachineInstr::MachineInstr(MachineFunction &MF, const MCInstrDesc &TID,
141 void MachineInstr::setDesc(const MCInstrDesc &TID) {
275 // Tie uses to defs as indicated in MCInstrDesc.
911 // Most opcodes have fixed constraints in their MCInstrDesc.
1096 const MCInstrDesc &MCID = getDesc();
1524 const MCInstrDesc &MCID = getDesc();
2154 const MCInstrDesc &MCID, bool IsIndirect,
2170 const MCInstrDesc
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/freebsd-current/contrib/llvm-project/llvm/lib/Target/X86/
H A DX86InstrInfo.h49 int getCondSrcNoFromDesc(const MCInstrDesc &MCID);
174 getRegClass(const MCInstrDesc &MCID, unsigned OpNum,
H A DX86FixupLEAs.cpp653 const MCInstrDesc &Desc = MI.getDesc();
716 const MCInstrDesc &ADDrr = TII->get(getADDrrFromLEA(Opcode));
724 const MCInstrDesc &ADDri =
/freebsd-current/contrib/llvm-project/llvm/lib/Target/MSP430/
H A DMSP430InstrInfo.cpp289 const MCInstrDesc &Desc = MI.getDesc();
/freebsd-current/contrib/llvm-project/llvm/lib/Target/CSKY/
H A DCSKYRegisterInfo.cpp110 const MCInstrDesc &Desc = MI->getDesc();
/freebsd-current/contrib/llvm-project/llvm/lib/Target/Hexagon/MCTargetDesc/
H A DHexagonMCInstrInfo.cpp255 MCInstrDesc const &HexagonMCInstrInfo::getDesc(MCInstrInfo const &MCII,
770 MCInstrDesc const &Desc = HexagonMCInstrInfo::getDesc(MCII, Inst);
941 MCInstrDesc const &Desc = getDesc(MCII, MCI);
1060 MCInstrDesc const &Desc = HexagonMCInstrInfo::getDesc(MCII, I);
H A DHexagonMCCodeEmitter.cpp20 #include "llvm/MC/MCInstrDesc.h"
463 const MCInstrDesc &MCID = HexagonMCInstrInfo::getDesc(MCII, MI);
475 const MCInstrDesc &NextD = HexagonMCInstrInfo::getDesc(MCII, NextI);
616 const MCInstrDesc &MCID = HexagonMCInstrInfo::getDesc(MCII, MI);
646 auto UsesGP = [](const MCInstrDesc &D) {
H A DHexagonMCChecker.cpp23 #include "llvm/MC/MCInstrDesc.h"
93 const MCInstrDesc &MCID = HexagonMCInstrInfo::getDesc(MCII, MCI);
473 MCInstrDesc const &Desc = HexagonMCInstrInfo::getDesc(MCII, *ProducerInst);
564 MCInstrDesc const &Desc = HexagonMCInstrInfo::getDesc(MCII, I);
/freebsd-current/contrib/llvm-project/llvm/lib/Target/LoongArch/MCTargetDesc/
H A DLoongArchMCCodeEmitter.cpp322 const MCInstrDesc &Desc = MCII.get(MI.getOpcode());
/freebsd-current/contrib/llvm-project/llvm/lib/Target/SystemZ/
H A DSystemZHazardRecognizer.cpp120 const MCInstrDesc &MID = MI->getDesc();
/freebsd-current/contrib/llvm-project/llvm/lib/Target/WebAssembly/
H A DWebAssemblyMCInstLower.cpp171 const MCInstrDesc &Desc = MI->getDesc();
/freebsd-current/contrib/llvm-project/llvm/lib/Target/RISCV/
H A DRISCVInstrInfo.h56 const MCInstrDesc &getBrCond(RISCVCC::CondCode CC) const;
H A DRISCVAsmPrinter.cpp896 const MCInstrDesc &MCID = MI->getDesc();
922 const MCInstrDesc &OutMCID = TII->get(OutMI.getOpcode());
977 const MCInstrDesc &OutMCID = TII->get(OutMI.getOpcode());
/freebsd-current/contrib/llvm-project/llvm/include/llvm/CodeGen/
H A DMachineInstr.h28 #include "llvm/MC/MCInstrDesc.h"
120 const MCInstrDesc *MCID; // Instruction descriptor.
301 /// MCInstrDesc. An explicit DebugLoc is supplied.
302 MachineInstr(MachineFunction &, const MCInstrDesc &TID, DebugLoc DL,
540 const MCInstrDesc &getDesc() const { return *MCID; }
848 /// API for querying MachineInstr properties. They are the same as MCInstrDesc
1563 /// For normal instructions, this is derived from the MCInstrDesc.
1609 /// MCInstrDesc. This method is for exceptional cases like inline asm.
1730 /// For all instructions, the property is encoded in MCInstrDesc::Flags
1731 /// (see MCInstrDesc
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/freebsd-current/contrib/llvm-project/llvm/lib/Target/Hexagon/
H A DHexagonEarlyIfConv.cpp740 const MCInstrDesc &D = HII->get(IfTrue ? Hexagon::J2_jumpt
797 const MCInstrDesc &D = HII->get(Opc);
920 const MCInstrDesc &D = HasBranch ? HII->get(Hexagon::J2_jump)

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