/freebsd-current/contrib/llvm-project/llvm/lib/Target/ARM/ |
H A D | ARMBaseInstrInfo.cpp | 53 #include "llvm/MC/MCInstrDesc.h" 207 const MCInstrDesc &MCID = MI.getDesc(); 620 const MCInstrDesc &MCID = MI.getDesc(); 672 const MCInstrDesc &MCID = MI.getDesc(); 783 const MCInstrDesc &MCID = MI.getDesc(); 2370 const MCInstrDesc &DefDesc = DefMI->getDesc(); 2634 const MCInstrDesc &Desc = MI.getDesc(); 3326 const MCInstrDesc &DefMCID = DefMI.getDesc(); 3336 const MCInstrDesc &UseMCID = UseMI.getDesc(); 3464 const MCInstrDesc [all...] |
H A D | ARMLowOverheadLoops.cpp | 71 #include "llvm/MC/MCInstrDesc.h" 107 const MCInstrDesc &MCID = MI.getDesc(); 824 const MCInstrDesc &MCID = MI.getDesc(); 833 const MCInstrDesc &MCID = MI.getDesc(); 839 const MCInstrDesc &MCID = MI.getDesc(); 1243 const MCInstrDesc &MCID = MI->getDesc();
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/freebsd-current/contrib/llvm-project/llvm/lib/Target/X86/MCTargetDesc/ |
H A D | X86MCCodeEmitter.cpp | 22 #include "llvm/MC/MCInstrDesc.h" 483 const MCInstrDesc &Desc = MCII.get(Opcode); 955 const MCInstrDesc &Desc = MCII.get(MI.getOpcode()); 1302 const MCInstrDesc &Desc = MCII.get(MI.getOpcode()); 1425 const MCInstrDesc &Desc = MCII.get(MI.getOpcode()); 1487 const MCInstrDesc &Desc = MCII.get(Opcode); 1504 const MCInstrDesc &Desc = MCII.get(Opcode);
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/freebsd-current/contrib/llvm-project/llvm/lib/Target/AMDGPU/ |
H A D | SIInstrInfo.h | 308 const MCInstrDesc &getIndirectRegWriteMovRelPseudo(unsigned VecSize, 312 const MCInstrDesc &getIndirectGPRIDXPseudo(unsigned VecSize, 325 bool findCommutedOpIndices(const MCInstrDesc &Desc, unsigned &SrcOpIdx0, 1220 const MCInstrDesc &getMCOpcodeFromPseudo(unsigned Opcode) const { 1303 const MCInstrDesc &getKillTerminatorFromPseudo(unsigned Opcode) const; 1336 const TargetRegisterClass *getRegClass(const MCInstrDesc &TID, unsigned OpNum,
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H A D | SIFoldOperands.cpp | 627 const MCInstrDesc &InstDesc = MI->getDesc(); 690 const MCInstrDesc &Desc = UseMI->getDesc(); 1026 const MCInstrDesc &UseDesc = UseMI->getDesc(); 1060 const MCInstrDesc &FoldDesc = OpToFold.getParent()->getDesc(); 1157 static void mutateCopyOp(MachineInstr &MI, const MCInstrDesc &NewDesc) { 1163 const MCInstrDesc &Desc = MI.getDesc(); 1772 const MCInstrDesc &InstDesc = UseMI->getDesc();
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/freebsd-current/contrib/llvm-project/llvm/lib/CodeGen/SelectionDAG/ |
H A D | ResourcePriorityQueue.cpp | 435 const MCInstrDesc &TID = TII->get(N->getMachineOpcode()); 537 const MCInstrDesc &TID = TII->get(N->getMachineOpcode());
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H A D | ScheduleDAGFast.cpp | 250 const MCInstrDesc &MCID = TII->get(N->getMachineOpcode()); 424 const MCInstrDesc &MCID = TII->get(N->getMachineOpcode()); 524 const MCInstrDesc &MCID = TII->get(Node->getMachineOpcode());
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/freebsd-current/contrib/llvm-project/llvm/lib/Target/AArch64/ |
H A D | AArch64ConditionalCompares.cpp | 630 const MCInstrDesc &MCID = TII->get(Opc); 687 const MCInstrDesc &MCID = TII->get(Opc);
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/freebsd-current/contrib/llvm-project/llvm/lib/Target/AVR/ |
H A D | AVRInstrInfo.cpp | 195 const MCInstrDesc &AVRInstrInfo::getBrCond(AVRCC::CondCodes CC) const { 485 const MCInstrDesc &Desc = get(Opcode);
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/freebsd-current/contrib/llvm-project/llvm/lib/Target/RISCV/MCTargetDesc/ |
H A D | RISCVMCCodeEmitter.cpp | 300 const MCInstrDesc &Desc = MCII.get(MI.getOpcode()); 390 MCInstrDesc const &Desc = MCII.get(MI.getOpcode());
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/freebsd-current/contrib/llvm-project/llvm/lib/CodeGen/ |
H A D | MachineInstr.cpp | 47 #include "llvm/MC/MCInstrDesc.h" 96 /// the MCInstrDesc. 97 MachineInstr::MachineInstr(MachineFunction &MF, const MCInstrDesc &TID, 141 void MachineInstr::setDesc(const MCInstrDesc &TID) { 275 // Tie uses to defs as indicated in MCInstrDesc. 911 // Most opcodes have fixed constraints in their MCInstrDesc. 1096 const MCInstrDesc &MCID = getDesc(); 1524 const MCInstrDesc &MCID = getDesc(); 2154 const MCInstrDesc &MCID, bool IsIndirect, 2170 const MCInstrDesc [all...] |
/freebsd-current/contrib/llvm-project/llvm/lib/Target/X86/ |
H A D | X86InstrInfo.h | 49 int getCondSrcNoFromDesc(const MCInstrDesc &MCID); 174 getRegClass(const MCInstrDesc &MCID, unsigned OpNum,
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H A D | X86FixupLEAs.cpp | 653 const MCInstrDesc &Desc = MI.getDesc(); 716 const MCInstrDesc &ADDrr = TII->get(getADDrrFromLEA(Opcode)); 724 const MCInstrDesc &ADDri =
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/freebsd-current/contrib/llvm-project/llvm/lib/Target/MSP430/ |
H A D | MSP430InstrInfo.cpp | 289 const MCInstrDesc &Desc = MI.getDesc();
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/freebsd-current/contrib/llvm-project/llvm/lib/Target/CSKY/ |
H A D | CSKYRegisterInfo.cpp | 110 const MCInstrDesc &Desc = MI->getDesc();
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/freebsd-current/contrib/llvm-project/llvm/lib/Target/Hexagon/MCTargetDesc/ |
H A D | HexagonMCInstrInfo.cpp | 255 MCInstrDesc const &HexagonMCInstrInfo::getDesc(MCInstrInfo const &MCII, 770 MCInstrDesc const &Desc = HexagonMCInstrInfo::getDesc(MCII, Inst); 941 MCInstrDesc const &Desc = getDesc(MCII, MCI); 1060 MCInstrDesc const &Desc = HexagonMCInstrInfo::getDesc(MCII, I);
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H A D | HexagonMCCodeEmitter.cpp | 20 #include "llvm/MC/MCInstrDesc.h" 463 const MCInstrDesc &MCID = HexagonMCInstrInfo::getDesc(MCII, MI); 475 const MCInstrDesc &NextD = HexagonMCInstrInfo::getDesc(MCII, NextI); 616 const MCInstrDesc &MCID = HexagonMCInstrInfo::getDesc(MCII, MI); 646 auto UsesGP = [](const MCInstrDesc &D) {
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H A D | HexagonMCChecker.cpp | 23 #include "llvm/MC/MCInstrDesc.h" 93 const MCInstrDesc &MCID = HexagonMCInstrInfo::getDesc(MCII, MCI); 473 MCInstrDesc const &Desc = HexagonMCInstrInfo::getDesc(MCII, *ProducerInst); 564 MCInstrDesc const &Desc = HexagonMCInstrInfo::getDesc(MCII, I);
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/freebsd-current/contrib/llvm-project/llvm/lib/Target/LoongArch/MCTargetDesc/ |
H A D | LoongArchMCCodeEmitter.cpp | 322 const MCInstrDesc &Desc = MCII.get(MI.getOpcode());
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/freebsd-current/contrib/llvm-project/llvm/lib/Target/SystemZ/ |
H A D | SystemZHazardRecognizer.cpp | 120 const MCInstrDesc &MID = MI->getDesc();
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/freebsd-current/contrib/llvm-project/llvm/lib/Target/WebAssembly/ |
H A D | WebAssemblyMCInstLower.cpp | 171 const MCInstrDesc &Desc = MI->getDesc();
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/freebsd-current/contrib/llvm-project/llvm/lib/Target/RISCV/ |
H A D | RISCVInstrInfo.h | 56 const MCInstrDesc &getBrCond(RISCVCC::CondCode CC) const;
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H A D | RISCVAsmPrinter.cpp | 896 const MCInstrDesc &MCID = MI->getDesc(); 922 const MCInstrDesc &OutMCID = TII->get(OutMI.getOpcode()); 977 const MCInstrDesc &OutMCID = TII->get(OutMI.getOpcode());
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/freebsd-current/contrib/llvm-project/llvm/include/llvm/CodeGen/ |
H A D | MachineInstr.h | 28 #include "llvm/MC/MCInstrDesc.h" 120 const MCInstrDesc *MCID; // Instruction descriptor. 301 /// MCInstrDesc. An explicit DebugLoc is supplied. 302 MachineInstr(MachineFunction &, const MCInstrDesc &TID, DebugLoc DL, 540 const MCInstrDesc &getDesc() const { return *MCID; } 848 /// API for querying MachineInstr properties. They are the same as MCInstrDesc 1563 /// For normal instructions, this is derived from the MCInstrDesc. 1609 /// MCInstrDesc. This method is for exceptional cases like inline asm. 1730 /// For all instructions, the property is encoded in MCInstrDesc::Flags 1731 /// (see MCInstrDesc [all...] |
/freebsd-current/contrib/llvm-project/llvm/lib/Target/Hexagon/ |
H A D | HexagonEarlyIfConv.cpp | 740 const MCInstrDesc &D = HII->get(IfTrue ? Hexagon::J2_jumpt 797 const MCInstrDesc &D = HII->get(Opc); 920 const MCInstrDesc &D = HasBranch ? HII->get(Hexagon::J2_jump)
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