| /freebsd-current/contrib/llvm-project/llvm/lib/Target/CSKY/ |
| H A D | CSKYISelDAGToDAG.cpp | 52 InlineAsm::ConstraintCode ConstraintID,
387 const SDValue &Op, const InlineAsm::ConstraintCode ConstraintID,
390 case InlineAsm::ConstraintCode::m:
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| /freebsd-current/contrib/llvm-project/llvm/lib/Target/Mips/ |
| H A D | MipsSERegisterInfo.cpp | 106 case InlineAsm::ConstraintCode::ZC: {
|
| H A D | MipsSEISelDAGToDAG.cpp | 1379 const SDValue &Op, InlineAsm::ConstraintCode ConstraintID,
1387 case InlineAsm::ConstraintCode::m:
1388 case InlineAsm::ConstraintCode::o:
1397 case InlineAsm::ConstraintCode::R:
1411 case InlineAsm::ConstraintCode::ZC:
|
| /freebsd-current/contrib/llvm-project/llvm/lib/Target/Hexagon/ |
| H A D | HexagonISelDAGToDAG.h | 87 InlineAsm::ConstraintCode ConstraintID,
|
| H A D | HexagonISelDAGToDAG.cpp | 958 const SDValue &Op, InlineAsm::ConstraintCode ConstraintID,
965 case InlineAsm::ConstraintCode::o: // Offsetable.
966 case InlineAsm::ConstraintCode::v: // Not offsetable.
967 case InlineAsm::ConstraintCode::m: // Memory.
|
| /freebsd-current/contrib/llvm-project/llvm/lib/Target/X86/ |
| H A D | X86ISelLowering.h | 1286 InlineAsm::ConstraintCode
1287 getInlineAsmMemConstraint(StringRef ConstraintCode) const override {
1288 if (ConstraintCode == "v")
1289 return InlineAsm::ConstraintCode::v;
1290 return TargetLowering::getInlineAsmMemConstraint(ConstraintCode);
|
| H A D | X86ISelDAGToDAG.cpp | 262 InlineAsm::ConstraintCode ConstraintID,
6446 const SDValue &Op, InlineAsm::ConstraintCode ConstraintID,
6452 case InlineAsm::ConstraintCode::o: // offsetable ??
6453 case InlineAsm::ConstraintCode::v: // not offsetable ??
6454 case InlineAsm::ConstraintCode::m: // memory
6455 case InlineAsm::ConstraintCode::X:
6456 case InlineAsm::ConstraintCode::p: // address
|
| /freebsd-current/contrib/llvm-project/llvm/lib/Target/AArch64/ |
| H A D | AArch64ISelLowering.h | 1237 InlineAsm::ConstraintCode
1238 getInlineAsmMemConstraint(StringRef ConstraintCode) const override {
1239 if (ConstraintCode == "Q")
1240 return InlineAsm::ConstraintCode::Q;
1244 return TargetLowering::getInlineAsmMemConstraint(ConstraintCode);
|
| /freebsd-current/contrib/llvm-project/llvm/lib/Target/RISCV/ |
| H A D | RISCVISelDAGToDAG.h | 47 InlineAsm::ConstraintCode ConstraintID,
|
| H A D | RISCVMergeBaseOffset.cpp | 430 if (Flags.getMemoryConstraintID() == InlineAsm::ConstraintCode::A)
|
| H A D | RISCVISelLowering.h | 574 InlineAsm::ConstraintCode
575 getInlineAsmMemConstraint(StringRef ConstraintCode) const override;
|
| H A D | RISCVISelDAGToDAG.cpp | 2195 const SDValue &Op, InlineAsm::ConstraintCode ConstraintID,
2200 case InlineAsm::ConstraintCode::o:
2201 case InlineAsm::ConstraintCode::m: {
2210 case InlineAsm::ConstraintCode::A:
|
| /freebsd-current/contrib/llvm-project/llvm/include/llvm/CodeGen/ |
| H A D | SelectionDAGISel.h | 101 InlineAsm::ConstraintCode ConstraintID,
|
| H A D | TargetLowering.h | 4805 std::string ConstraintCode; member in struct:llvm::TargetLoweringBase::TargetLowering::AsmOperandInfo
4853 /// AsmOperandInfo, setting OpInfo.ConstraintCode and OpInfo.ConstraintType.
4885 virtual InlineAsm::ConstraintCode
4886 getInlineAsmMemConstraint(StringRef ConstraintCode) const {
4887 if (ConstraintCode == "m")
4888 return InlineAsm::ConstraintCode::m;
4889 if (ConstraintCode == "o")
4890 return InlineAsm::ConstraintCode::o;
4891 if (ConstraintCode == "X")
4892 return InlineAsm::ConstraintCode
[all...] |
| /freebsd-current/contrib/llvm-project/llvm/lib/Target/M68k/ |
| H A D | M68kISelLowering.cpp | 206 InlineAsm::ConstraintCode
207 M68kTargetLowering::getInlineAsmMemConstraint(StringRef ConstraintCode) const {
208 return StringSwitch<InlineAsm::ConstraintCode>(ConstraintCode)
209 .Case("Q", InlineAsm::ConstraintCode::Q)
210 // We borrow ConstraintCode::Um for 'U'.
211 .Case("U", InlineAsm::ConstraintCode::Um)
212 .Default(TargetLowering::getInlineAsmMemConstraint(ConstraintCode));
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| /freebsd-current/contrib/llvm-project/llvm/lib/Target/ARM/ |
| H A D | ARMISelDAGToDAG.cpp | 335 InlineAsm::ConstraintCode ConstraintID,
5865 const SDValue &Op, InlineAsm::ConstraintCode ConstraintID,
5870 case InlineAsm::ConstraintCode::m:
5871 case InlineAsm::ConstraintCode::o:
5872 case InlineAsm::ConstraintCode::Q:
5873 case InlineAsm::ConstraintCode::Um:
5874 case InlineAsm::ConstraintCode::Un:
5875 case InlineAsm::ConstraintCode::Uq:
5876 case InlineAsm::ConstraintCode::Us:
5877 case InlineAsm::ConstraintCode
[all...] |
| /freebsd-current/contrib/llvm-project/llvm/lib/CodeGen/SelectionDAG/ |
| H A D | FunctionLoweringInfo.cpp | 196 TLI->getRegForInlineAsmConstraint(TRI, Op.ConstraintCode,
|
| H A D | SelectionDAGBuilder.cpp | 9014 TLI.getRegForInlineAsmConstraint(TRI, OpInfo.ConstraintCode,
9017 TLI.getRegForInlineAsmConstraint(TRI, MatchingOpInfo.ConstraintCode,
9100 &TRI, RefOpInfo.ConstraintCode, RefOpInfo.ConstraintVT);
9298 return emitInlineAsmError(Call, "constraint '" + Twine(T.ConstraintCode) +
9432 Twine(OpInfo.ConstraintCode) +
9459 const InlineAsm::ConstraintCode ConstraintID =
9460 TLI.getInlineAsmMemConstraint(OpInfo.ConstraintCode);
9461 assert(ConstraintID != InlineAsm::ConstraintCode::Unknown &&
9477 Twine(OpInfo.ConstraintCode) + "'");
9558 TLI.LowerAsmOperandForConstraint(InOperandVal, OpInfo.ConstraintCode,
[all...] |
| H A D | TargetLowering.cpp | 5592 assert(!ConstraintCode.empty() && "No known constraint!");
5593 return isdigit(static_cast<unsigned char>(ConstraintCode[0]));
5599 assert(!ConstraintCode.empty() && "No known constraint!");
5600 return atoi(ConstraintCode.c_str());
5771 getRegForInlineAsmConstraint(TRI, OpInfo.ConstraintCode,
5774 getRegForInlineAsmConstraint(TRI, Input.ConstraintCode,
5961 /// AsmOperandInfo, setting OpInfo.ConstraintCode and OpInfo.ConstraintType.
5969 OpInfo.ConstraintCode = OpInfo.Codes[0];
5970 OpInfo.ConstraintType = getConstraintType(OpInfo.ConstraintCode);
5990 OpInfo.ConstraintCode
[all...] |
| /freebsd-current/contrib/llvm-project/llvm/lib/Target/AVR/ |
| H A D | AVRISelLowering.cpp | 2523 InlineAsm::ConstraintCode
2524 AVRTargetLowering::getInlineAsmMemConstraint(StringRef ConstraintCode) const {
2527 switch (ConstraintCode[0]) {
2529 return InlineAsm::ConstraintCode::Q;
2531 return TargetLowering::getInlineAsmMemConstraint(ConstraintCode);
|
| /freebsd-current/contrib/llvm-project/llvm/lib/CodeGen/ |
| H A D | TargetInstrInfo.cpp | 588 F.setMemConstraint(InlineAsm::ConstraintCode::m);
1715 InlineAsm::ConstraintCode MCID = F.getMemoryConstraintID();
|
| /freebsd-current/contrib/llvm-project/llvm/lib/Target/LoongArch/ |
| H A D | LoongArchISelLowering.cpp | 4679 InlineAsm::ConstraintCode LoongArchTargetLowering::getInlineAsmMemConstraint(
4680 StringRef ConstraintCode) const {
4681 return StringSwitch<InlineAsm::ConstraintCode>(ConstraintCode)
4682 .Case("k", InlineAsm::ConstraintCode::k)
4683 .Case("ZB", InlineAsm::ConstraintCode::ZB)
4684 .Case("ZC", InlineAsm::ConstraintCode::ZC)
4685 .Default(TargetLowering::getInlineAsmMemConstraint(ConstraintCode));
|
| /freebsd-current/contrib/llvm-project/llvm/lib/Target/AMDGPU/ |
| H A D | AMDGPUTargetTransformInfo.cpp | 872 TRI, TC.ConstraintCode, TC.ConstraintVT).second;
|
| /freebsd-current/contrib/llvm-project/llvm/lib/Target/PowerPC/ |
| H A D | PPCISelDAGToDAG.cpp | 390 InlineAsm::ConstraintCode ConstraintID,
397 case InlineAsm::ConstraintCode::es:
398 case InlineAsm::ConstraintCode::m:
399 case InlineAsm::ConstraintCode::o:
400 case InlineAsm::ConstraintCode::Q:
401 case InlineAsm::ConstraintCode::Z:
402 case InlineAsm::ConstraintCode::Zy:
|
| /freebsd-current/contrib/llvm-project/llvm/lib/Target/NVPTX/ |
| H A D | NVPTXISelDAGToDAG.cpp | 3628 const SDValue &Op, InlineAsm::ConstraintCode ConstraintID,
3634 case InlineAsm::ConstraintCode::m: // memory
|