Searched refs:BitVector (Results 151 - 175 of 285) sorted by relevance

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/freebsd-current/contrib/llvm-project/llvm/lib/Target/Hexagon/
H A DHexagonBlockRanges.h12 #include "llvm/ADT/BitVector.h"
174 BitVector Reserved;
/freebsd-current/contrib/llvm-project/llvm/lib/Target/AMDGPU/
H A DR600InstrInfo.h214 void reserveIndirectRegisters(BitVector &Reserved,
/freebsd-current/contrib/llvm-project/llvm/tools/llvm-pdbutil/
H A DPrettyClassLayoutGraphicalDumper.cpp45 const BitVector &UseMap = Layout.usedBytes();
/freebsd-current/contrib/llvm-project/llvm/lib/CodeGen/
H A DRegAllocBasic.cpp71 BitVector UsableRegs;
H A DSpillPlacement.cpp30 #include "llvm/ADT/BitVector.h"
353 void SpillPlacement::prepare(BitVector &RegBundles) {
H A DScheduleDAG.cpp605 BitVector VisitedBack;
679 void ScheduleDAGTopologicalSort::Shift(BitVector& Visited, int LowerBound,
H A DSwitchLoweringUtils.cpp325 BitVector Dests(FuncInfo.MF->getNumBlockIDs());
374 BitVector Dests(FuncInfo.MF->getNumBlockIDs());
/freebsd-current/contrib/llvm-project/llvm/lib/Target/ARM/
H A DARMBaseRegisterInfo.h162 BitVector getReservedRegs(const MachineFunction &MF) const override;
/freebsd-current/contrib/llvm-project/llvm/utils/TableGen/
H A DCodeGenInstruction.h16 #include "llvm/ADT/BitVector.h"
112 BitVector DoNotEncode;
H A DRegisterBankEmitter.cpp17 #include "llvm/ADT/BitVector.h"
202 BitVector BV(RegisterClassHierarchy.getRegClasses().size());
H A DRegisterInfoEmitter.cpp22 #include "llvm/ADT/BitVector.h"
589 // Print a BitVector as a sequence of hex numbers using a little-endian mapping.
592 const BitVector &Bits,
606 BitVector Values;
1325 BitVector MaskBV(RegisterClasses.size());
1448 llvm::BitVector InAllocClass(Regs.size() + 1, false);
1690 BitVector Covered = RegBank.computeCoveredRegisters(*Regs);
1855 const BitVector &SubClasses = RC.getSubClasses();
/freebsd-current/contrib/llvm-project/llvm/lib/Target/AArch64/
H A DAArch64RegisterInfo.cpp21 #include "llvm/ADT/BitVector.h"
404 BitVector
409 BitVector Reserved(getNumRegs());
465 BitVector
467 BitVector Reserved = getStrictlyReservedRegs(MF);
H A DAArch64SpeculationHardening.cpp96 #include "llvm/ADT/BitVector.h"
146 BitVector RegsNeedingCSDBBeforeUse;
147 BitVector RegsAlreadyMasked;
/freebsd-current/contrib/llvm-project/clang/lib/Analysis/
H A DUninitializedValues.cpp29 #include "llvm/ADT/BitVector.h"
839 llvm::BitVector &wasAnalyzed,
876 llvm::BitVector hadUse;
938 llvm::BitVector previouslyVisited(cfg.getNumBlockIDs());
940 llvm::BitVector wasAnalyzed(cfg.getNumBlockIDs(), false);
/freebsd-current/contrib/llvm-project/clang/include/clang/Serialization/
H A DModuleFile.h23 #include "llvm/ADT/BitVector.h"
190 llvm::BitVector SearchPathUsage;
/freebsd-current/contrib/llvm-project/clang/lib/Format/
H A DUnwrappedLineParser.h24 #include "llvm/ADT/BitVector.h"
324 llvm::BitVector DeclarationScopeStack;
/freebsd-current/contrib/llvm-project/llvm/lib/Target/PowerPC/
H A DPPCRegisterInfo.h93 BitVector getReservedRegs(const MachineFunction &MF) const override;
/freebsd-current/contrib/llvm-project/llvm/lib/Target/WebAssembly/
H A DWebAssemblyMachineFunctionInfo.h48 BitVector VRegStackified;
H A DWebAssemblyRegColoring.cpp286 BitVector UsedColors(SortedIntervals.size());
/freebsd-current/contrib/llvm-project/llvm/include/llvm/CodeGen/
H A DMachineRegisterInfo.h17 #include "llvm/ADT/BitVector.h"
134 BitVector UsedPhysRegMask;
140 BitVector ReservedRegs;
899 const BitVector &getUsedPhysRegsMask() const { return UsedPhysRegMask; }
945 const BitVector &getReservedRegs() const {
H A DScheduleDAG.h18 #include "llvm/ADT/BitVector.h"
718 BitVector Visited;
727 void Shift(BitVector& Visited, int LowerBound, int UpperBound);
/freebsd-current/contrib/llvm-project/llvm/lib/ProfileData/Coverage/
H A DCoverageMapping.cpp226 Expected<BitVector> CounterMappingContext::evaluateBitmap(
236 // Mask each bitmap byte into the BitVector. Go in reverse so that the
238 BitVector Result(SizeInBits, false);
252 const BitVector &ExecutedTestVectorBitmap;
281 MCDCRecordProcessor(const BitVector &Bitmap,
348 void findExecutedTestVectors(const BitVector &ExecutedTestVectorBitmap) {
480 const BitVector &ExecutedTestVectorBitmap,
840 Expected<BitVector> ExecutedTestVectorBitmap =
/freebsd-current/contrib/llvm-project/llvm/lib/Target/VE/
H A DVERegisterInfo.cpp16 #include "llvm/ADT/BitVector.h"
66 BitVector VERegisterInfo::getReservedRegs(const MachineFunction &MF) const {
67 BitVector Reserved(getNumRegs());
/freebsd-current/contrib/llvm-project/llvm/lib/DebugInfo/PDB/
H A DUDTLayout.cpp11 #include "llvm/ADT/BitVector.h"
284 BitVector ChildBytes = Child->usedBytes();
/freebsd-current/contrib/llvm-project/lld/MachO/
H A DInputSection.h19 #include "llvm/ADT/BitVector.h"
265 llvm::BitVector live;

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