Searched refs:BIT (Results 226 - 250 of 579) sorted by relevance

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/freebsd-current/sys/contrib/dev/mediatek/mt76/
H A Dmt792x_debugfs.c79 ctrl = BIT(31) | BIT(11) | (i << 24);
82 if (val & BIT(j))
H A Dmt76x02_beacon.c82 dev->mt76.beacon_mask |= BIT(mvif->idx);
84 dev->mt76.beacon_mask &= ~BIT(mvif->idx);
143 if (!(dev->mt76.beacon_mask & BIT(mvif->idx)))
163 if (!(dev->mt76.beacon_mask & BIT(mvif->idx)))
/freebsd-current/sys/dev/axgbe/
H A Dxgbe-i2c.c123 #define XGBE_INTR_RX_FULL BIT(IC_RAW_INTR_STAT_RX_FULL_INDEX)
124 #define XGBE_INTR_TX_EMPTY BIT(IC_RAW_INTR_STAT_TX_EMPTY_INDEX)
125 #define XGBE_INTR_TX_ABRT BIT(IC_RAW_INTR_STAT_TX_ABRT_INDEX)
126 #define XGBE_INTR_STOP_DET BIT(IC_RAW_INTR_STAT_STOP_DET_INDEX)
132 #define XGBE_I2C_READ BIT(8)
133 #define XGBE_I2C_STOP BIT(9)
/freebsd-current/contrib/wpa/src/ap/
H A Dieee802_11_ht.c257 (bc_ie->coex_param & BIT(0)) ? "[InfoReq]" : "",
258 (bc_ie->coex_param & BIT(1)) ? "[40MHzIntolerant]" : "",
259 (bc_ie->coex_param & BIT(2)) ? "[20MHzBSSWidthReq]" : "",
260 (bc_ie->coex_param & BIT(3)) ? "[OBSSScanExemptionReq]" : "",
261 (bc_ie->coex_param & BIT(4)) ?
263 (bc_ie->coex_param & (BIT(5) | BIT(6) | BIT(7))) ?
H A Dgas_serv.h69 (BIT(29) << MBO_ANQP_SUBTYPE_CELL_CONN_PREF)
/freebsd-current/contrib/wpa/src/drivers/
H A Ddriver_hostap.h198 #define HOSTAP_CRYPT_FLAG_SET_TX_KEY BIT(0)
199 #define HOSTAP_CRYPT_FLAG_PERMANENT BIT(1)
/freebsd-current/sys/contrib/dev/mediatek/mt76/mt76x2/
H A Dmcu.c64 val = BIT(31);
87 msg.channel |= cpu_to_le32(BIT(31));
H A Deeprom.h68 if (!(val & BIT(15)))
/freebsd-current/sys/dev/amdgpio/
H A Damdgpio.c87 if (val & BIT(OUTPUT_ENABLE_OFF))
228 val &= ~BIT(OUTPUT_ENABLE_OFF);
231 val |= BIT(OUTPUT_ENABLE_OFF);
265 if (val & BIT(OUTPUT_VALUE_OFF))
270 if (val & BIT(PIN_STS_OFF))
304 val &= ~BIT(OUTPUT_VALUE_OFF);
306 val |= BIT(OUTPUT_VALUE_OFF);
338 val = val ^ BIT(OUTPUT_VALUE_OFF);
/freebsd-current/sys/dev/iavf/
H A Dvirtchnl.h94 VIRTCHNL_LINK_SPEED_100MB = BIT(VIRTCHNL_LINK_SPEED_100MB_SHIFT),
95 VIRTCHNL_LINK_SPEED_1GB = BIT(VIRTCHNL_LINK_SPEED_1000MB_SHIFT),
96 VIRTCHNL_LINK_SPEED_10GB = BIT(VIRTCHNL_LINK_SPEED_10GB_SHIFT),
97 VIRTCHNL_LINK_SPEED_40GB = BIT(VIRTCHNL_LINK_SPEED_40GB_SHIFT),
98 VIRTCHNL_LINK_SPEED_20GB = BIT(VIRTCHNL_LINK_SPEED_20GB_SHIFT),
99 VIRTCHNL_LINK_SPEED_25GB = BIT(VIRTCHNL_LINK_SPEED_25GB_SHIFT),
100 VIRTCHNL_LINK_SPEED_2_5GB = BIT(VIRTCHNL_LINK_SPEED_2_5GB_SHIFT),
101 VIRTCHNL_LINK_SPEED_5GB = BIT(VIRTCHNL_LINK_SPEED_5GB_SHIFT),
/freebsd-current/sys/dev/qat/qat_hw/qat_c4xxx/
H A Dadf_c4xxx_ae_config.c29 if (mask & BIT(i))
42 if (au_mask == BIT(0))
/freebsd-current/sys/contrib/dev/mediatek/mt76/mt7615/
H A Dpci_init.c47 mt76_clear(dev, MT_MCU_CIRQ_IRQ_SEL(4), BIT(1));
48 mt76_set(dev, MT_MCU_CIRQ_IRQ_SEL(4), BIT(1));
/freebsd-current/sys/contrib/dev/iwlwifi/cfg/
H A D9000.c51 .ht40_bands = BIT(NL80211_BAND_2GHZ) | BIT(NL80211_BAND_5GHZ),
H A D8000.c55 .ht40_bands = BIT(NL80211_BAND_2GHZ) | BIT(NL80211_BAND_5GHZ),
/freebsd-current/sys/arm/mv/clk/
H A Da37x0_xtal.c47 #define BIT(x) (1 << (x)) macro
50 #define NB_GPIO1_MPP1_9 BIT(9)
/freebsd-current/sys/contrib/dev/athk/ath10k/
H A Dwmi.h523 BIT((svc_id) % (sizeof(u32))))
533 BIT(((((svc_id) - (len)) % 28) & 0x1f) + 4))
2741 WMI_10_2_RX_BATCH_MODE = BIT(0),
2742 WMI_10_2_ATF_CONFIG = BIT(1),
2743 WMI_10_2_COEX_GPIO = BIT(3),
2744 WMI_10_2_BSS_CHAN_INFO = BIT(6),
2745 WMI_10_2_PEER_STATS = BIT(7),
2759 #define NUM_UNITS_IS_NUM_VDEVS BIT(0)
2760 #define NUM_UNITS_IS_NUM_PEERS BIT(1)
2761 #define NUM_UNITS_IS_NUM_ACTIVE_PEERS BIT(
[all...]
/freebsd-current/sys/contrib/dev/athk/ath12k/
H A Dwmi.h1171 WMI_PEER_EXT_EHT = BIT(0),
1172 WMI_PEER_EXT_320MHZ = BIT(1),
2248 #define ATH12K_11B_SUPPORT BIT(0)
2249 #define ATH12K_11G_SUPPORT BIT(1)
2250 #define ATH12K_11A_SUPPORT BIT(2)
2251 #define ATH12K_11N_SUPPORT BIT(3)
2252 #define ATH12K_11AC_SUPPORT BIT(4)
2253 #define ATH12K_11AX_SUPPORT BIT(5)
2748 #define WMI_VDEV_START_HIDDEN_SSID BIT(0)
2749 #define WMI_VDEV_START_PMF_ENABLED BIT(
[all...]
H A Dmac.h34 #define IEEE80211_DISABLE_VHT_MCS_SUPPORT_0_11 BIT(24)
/freebsd-current/contrib/wpa/src/eapol_supp/
H A Deapol_supp_sm.h33 #define EAPOL_REQUIRE_KEY_UNICAST BIT(0)
34 #define EAPOL_REQUIRE_KEY_BROADCAST BIT(1)
64 #define EAPOL_LOCAL_WPS_IN_USE BIT(0)
65 #define EAPOL_PEER_IS_WPS20_AP BIT(1)
/freebsd-current/sys/dev/gve/
H A Dgve_adminq.h202 #define GVE_CAP1(a) BIT((int) a)
203 #define GVE_CAP2(a) BIT(((int) a) - 64)
204 #define GVE_CAP3(a) BIT(((int) a) - 128)
205 #define GVE_CAP4(a) BIT(((int) a) - 192)
/freebsd-current/sys/dev/iicbus/rtc/
H A Dpcf85063.c48 #define BIT(x) (1 << (x)) macro
53 #define PCF85063_CTRL1_TIME_FORMAT BIT(1)
54 #define PCF85063_CTRL1_RTC_CLK_STOP BIT(5)
55 #define PCF85063_TIME_REG_OSC_STOP BIT(7)
H A Drx8803.c48 #define BIT(x) (1 << (x)) macro
54 #define RX8803_FLAGS_V1F BIT(0)
55 #define RX8803_FLAGS_V2F BIT(1)
57 #define RX8803_CTRL_DISABLE BIT(0)
/freebsd-current/sys/dev/mlx5/mlx5_fpga/
H A Dcmd.h41 MLX5_FPGA_QPC_STATE = BIT(0),
/freebsd-current/sys/dev/qat/include/common/
H A Dadf_gen4_hw_data.h28 #define ADF_WQM_CSR_RPRESETCTL_RESET BIT(0)
30 #define ADF_WQM_CSR_RPRESETSTS_STATUS BIT(0)
35 #define ADF_WQM_CSR_RPRESETCTL_MASK (BIT(3) - 1)
38 #define ADF_WQM_CSR_RPRESETSTS_MASK (BIT(0))
/freebsd-current/sys/contrib/dev/mediatek/mt76/mt7996/
H A Dcoredump.c135 mt76_clear(dev, MT_MCU_WM_EXCP_PC_CTRL, BIT(0));
136 mt76_clear(dev, MT_MCU_WM_EXCP_LR_CTRL, BIT(0));
157 mt76_set(dev, MT_MCU_WM_EXCP_PC_CTRL, BIT(0));
158 mt76_set(dev, MT_MCU_WM_EXCP_LR_CTRL, BIT(0));

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