Searched refs:setReg (Results 126 - 134 of 134) sorted by relevance

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/freebsd-13-stable/contrib/llvm-project/llvm/lib/Target/AMDGPU/
H A DSIRegisterInfo.cpp1429 SOffset.setReg(FrameReg);
H A DSIISelLowering.cpp3900 Src0.setReg(RegOp0);
3906 Src1.setReg(RegOp1);
3912 Src2.setReg(RegOp2);
/freebsd-13-stable/contrib/llvm-project/llvm/lib/Target/X86/
H A DX86InstructionSelector.cpp262 I.getOperand(1).setReg(ExtSrc);
H A DX86FastISel.cpp3958 MO.setReg(IndexReg);
/freebsd-13-stable/contrib/llvm-project/llvm/lib/Target/AMDGPU/AsmParser/
H A DAMDGPUAsmParser.cpp5029 Inst.getOperand(OperandIdx[2]).setReg(AMDGPU::NoRegister);
5030 Inst.getOperand(OperandIdx[3]).setReg(AMDGPU::NoRegister);
/freebsd-13-stable/contrib/llvm-project/llvm/lib/Target/Hexagon/
H A DHexagonConstPropagation.cpp3140 O.setReg(ToReg);
H A DHexagonInstrInfo.cpp753 Loop->getOperand(1).setReg(NewLoopCount);
/freebsd-13-stable/contrib/llvm-project/llvm/lib/Target/ARM/Disassembler/
H A DARMDisassembler.cpp900 I->setReg(0);
902 I->setReg(ARM::CPSR);
/freebsd-13-stable/contrib/llvm-project/llvm/lib/Target/ARM/
H A DARMISelLowering.cpp10801 MIB->getOperand(5).setReg(ARM::CPSR);
11391 MO.setReg(ARM::CPSR);

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