Searched refs:isReg (Results 76 - 100 of 347) sorted by relevance

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/freebsd-13-stable/contrib/llvm-project/llvm/lib/Target/BPF/
H A DBPFMISimplifyPatchable.cpp134 if (Opnd.isReg() && Opnd.getReg() == I->getReg())
264 if (!MI.getOperand(0).isReg() || !MI.getOperand(1).isReg())
/freebsd-13-stable/contrib/llvm-project/llvm/lib/CodeGen/
H A DLiveRangeEdit.cpp114 if (!MO.isReg() || !MO.getReg() || !MO.readsReg())
294 if (VRM && MI->getOperand(0).isReg() && MI->getOperand(0).isDef() &&
311 if (!MOI->isReg())
354 if (MO.isReg() && Register::isPhysicalRegister(MO.getReg()))
H A DLiveRegUnits.cpp58 if (!MOP.isReg() || !MOP.readsReg())
H A DMachineCopyPropagation.cpp455 if (&MIUse != &Use && MIUse.isReg() && MIUse.isImplicit() &&
479 if (!MOUse.isReg() || MOUse.isTied() || MOUse.isUndef() || MOUse.isDef() ||
598 if (!MO.isReg() || !MO.readsReg())
621 if (!MO.isReg() || !MO.isDef())
636 if (MO.isReg() && MO.isEarlyClobber()) {
654 if (!MO.isReg())
756 if (!MODef.isReg() || MODef.isUse())
831 if (MO.isReg() && MO.isEarlyClobber()) {
840 if (!MO.isReg())
H A DMachineCSE.cpp169 if (!MO.isReg() || !MO.isUse())
238 if (!MO.isReg() || !MO.getReg())
284 if (!MO.isReg() || MO.isDef())
303 if (!MO.isReg() || !MO.isDef())
380 if (!MO.isReg() || !MO.isDef())
467 if (MO.isReg() && MO.isUse() && Register::isVirtualRegister(MO.getReg())) {
597 if (!MO.isReg() || !MO.isDef())
785 if (use.isReg() && !Register::isVirtualRegister(use.getReg()))
H A DRegisterScavenging.cpp135 if (!MO.isReg())
206 if (!MO.isReg())
331 if (!MO.isReg() || MO.isUndef() || !MO.getReg())
434 if (MO.isReg() && Register::isVirtualRegister(MO.getReg())) {
545 if (MO.isReg() && MO.getReg() != 0 && !(MO.isUse() && MO.isUndef()) &&
696 if (!MO.isReg())
718 if (!MO.isReg())
741 if (!MO.isReg() || !Register::isVirtualRegister(MO.getReg()))
/freebsd-13-stable/contrib/llvm-project/llvm/lib/Target/Hexagon/MCTargetDesc/
H A DHexagonInstPrinter.cpp68 if (MO.isReg()) {
/freebsd-13-stable/contrib/llvm-project/llvm/lib/Target/MSP430/MCTargetDesc/
H A DMSP430InstPrinter.cpp56 if (Op.isReg()) {
H A DMSP430MCCodeEmitter.cpp105 if (MO.isReg())
124 assert(MO1.isReg() && "Register operand expected");
/freebsd-13-stable/contrib/llvm-project/llvm/lib/Target/Mips/MCTargetDesc/
H A DMipsELFStreamer.cpp46 if (!Op.isReg())
/freebsd-13-stable/contrib/llvm-project/llvm/lib/Target/Mips/
H A DMips16RegisterInfo.cpp107 if ((MI.getNumOperands()> OpNo+2) && MI.getOperand(OpNo+2).isReg())
/freebsd-13-stable/contrib/llvm-project/llvm/lib/Target/PowerPC/
H A DPPCBranchCoalescing.cpp349 if (Op1.isReg() &&
364 if (Op1.isReg() && Op2.isReg() &&
466 if (Use.isReg() && Register::isVirtualRegister(Use.getReg())) {
/freebsd-13-stable/contrib/llvm-project/llvm/lib/Target/AArch64/
H A DAArch64CollectLOH.cpp486 if (!MO.isReg() || !MO.isDef())
497 if (!MO.isReg() || !MO.readsReg())
547 assert(Def.isReg() && Def.isDef() && "Expected reg def");
548 assert(Op.isReg() && Op.isUse() && "Expected reg use");
H A DAArch64StorePairSuppress.cpp155 BaseOp->isReg()) {
/freebsd-13-stable/contrib/llvm-project/llvm/lib/Target/AMDGPU/
H A DR600AsmPrinter.cpp58 if (!MO.isReg())
H A DSIPostRABundler.cpp76 if (!Op.isReg())
H A DGCNHazardRecognizer.cpp473 if (Op.isReg())
558 if (!Use.isReg())
595 if (!Use.isReg() || TRI.isVGPR(MF.getRegInfo(), Use.getReg()))
617 if (!Use.isReg() || !TRI->isVGPR(MF.getRegInfo(), Use.getReg()))
697 (!SOffset || !SOffset->isReg()))
779 if (Op.isReg() && Op.isDef()) {
795 if (!LaneSelectOp->isReg() || !TRI->isSGPRReg(MRI, LaneSelectOp->getReg()))
838 if (!Use.isReg() || TRI->isVGPR(MF.getRegInfo(), Use.getReg()))
1223 if (!Use.isReg() || !TRI.isVGPR(MF.getRegInfo(), Use.getReg()))
1243 if (!Op.isReg() || !TR
[all...]
/freebsd-13-stable/contrib/llvm-project/llvm/lib/Target/Sparc/
H A DDelaySlotFiller.cpp253 if (!MO.isReg())
303 assert(Reg.isReg() && "CALL first operand is not a register.");
310 assert(Operand1.isReg() && "CALLrr second operand is not a register.");
324 if (!MO.isReg())
/freebsd-13-stable/contrib/llvm-project/llvm/lib/Target/SystemZ/
H A DSystemZMCInstLower.cpp99 if (!MO.isReg() || !MO.isImplicit())
/freebsd-13-stable/contrib/llvm-project/llvm/lib/Target/WebAssembly/
H A DWebAssemblyFixBrTableDefaults.cpp76 assert(Cond.size() == 2 && Cond[1].isReg() && "Unexpected condition info");
/freebsd-13-stable/contrib/llvm-project/llvm/lib/Target/Hexagon/
H A DHexagonAsmPrinter.cpp131 if (!MO.isReg())
165 if (Base.isReg())
375 assert(Rt.isReg() && "Expected register and none was found");
386 assert(Rt.isReg() && "Expected register and none was found");
398 assert(Rt.isReg() && "Expected register and none was found");
410 assert(Rs.isReg() && "Expected register and none was found");
595 assert(Rt.isReg() && "Expected register and none was found");
607 assert(Inst.getOperand(0).isReg() &&
620 assert (Inst.getOperand(0).isReg() &&
H A DHexagonCopyToCombine.cpp134 assert(Op0.isReg() && Op1.isReg());
147 assert(Op0.isReg());
240 if (!Op.isReg() || Op.getReg() != RegNotKilled || !Op.isKill())
258 return MO.isReg() ? MO.getReg() : Register();
409 if (!Op.isReg() || !Op.isUse() || !Op.getReg())
442 if (Op.isReg()) {
612 bool IsHiReg = HiOperand.isReg();
613 bool IsLoReg = LoOperand.isReg();
/freebsd-13-stable/contrib/llvm-project/llvm/include/llvm/CodeGen/
H A DMachineInstr.h489 return Op.isReg() && Op.getReg() == Reg;
496 return Op.isReg() && Op.getReg() == Reg;
1152 return isDebugValue() && getDebugOperand(0).isReg() && isDebugOffsetImm();
1162 return isDebugValue() && getDebugOperand(0).isReg() &&
1456 if (!MO.isReg() || !MO.isDef() || !MO.isTied())
1469 if (!MO.isReg() || !MO.isUse() || !MO.isTied())
1736 if (MO.isReg() && MO.isTied()) {
1764 if (MO.isReg())
/freebsd-13-stable/contrib/llvm-project/llvm/utils/TableGen/
H A DCodeGenInstruction.h365 bool isReg() const { return Kind == K_Reg; } function in struct:llvm::CodeGenInstAlias::ResultOperand
370 Record *getRegister() const { assert(isReg()); return R; }
/freebsd-13-stable/contrib/llvm-project/llvm/lib/Target/ARM/
H A DThumb2ITBlockPass.cpp88 if (!MO.isReg())
115 if (!MO.isReg() || MO.isDef() || !MO.isKill())

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