/freebsd-13-stable/contrib/llvm-project/llvm/include/llvm/ADT/ |
H A D | APFloat.h | 1188 APFloat Tmp(V); 1189 Tmp.convert(getSemantics(), APFloat::rmNearestTiesToEven, &ignored); 1190 return bitwiseIsEqual(Tmp);
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/freebsd-13-stable/contrib/llvm-project/llvm/lib/CodeGen/ |
H A D | RDFLiveness.cpp | 207 std::vector<NodeId> Tmp(Owners.begin(), Owners.end()); 208 llvm::sort(Tmp, Less); 230 for (NodeId T : Tmp) {
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/freebsd-13-stable/contrib/llvm-project/llvm/lib/ExecutionEngine/Orc/ |
H A D | LLJIT.cpp | 687 auto Tmp = std::make_unique<MachOPlatform>( local 691 auto &MP = *Tmp; 692 J.getExecutionSession().setPlatform(std::move(Tmp));
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/freebsd-13-stable/contrib/llvm-project/llvm/lib/Transforms/Scalar/ |
H A D | Scalarizer.cpp | 105 ValueVector Tmp; member in class:__anon4710::Scatterer 267 Tmp.resize(Size, nullptr); 276 ValueVector &CV = (CachePtr ? *CachePtr : Tmp);
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/freebsd-13-stable/contrib/llvm-project/llvm/lib/Target/Hexagon/ |
H A D | BitTracker.cpp | 261 RegisterCell Tmp(W-Sh); 262 // Tmp = [0..W-Sh-1]. 264 Tmp[i] = Bits[i]; 268 // Copy Tmp to [Sh..W-1]. 270 Bits[i+Sh] = Tmp.Bits[i];
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H A D | HexagonISelLoweringHVX.cpp | 443 ArrayRef<Constant*> Tmp((Constant**)Consts.begin(), 445 Constant *CV = ConstantVector::get(Tmp); 1084 SmallVector<Constant*, 128> Tmp; local 1089 Tmp.push_back(ConstantInt::get(Int8Ty, 1ull << j)); 1091 Constant *CV = ConstantVector::get(Tmp);
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/freebsd-13-stable/contrib/llvm-project/llvm/lib/Target/Mips/ |
H A D | MipsInstructionSelector.cpp | 483 Register Tmp = MRI.createVirtualRegister(&Mips::GPR32RegClass); local 484 if (!buildUnalignedLoad(I, Mips::LWL, Tmp, BaseAddr, SignedOffset + 3, 488 BaseAddr, SignedOffset, Tmp, MMO))
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H A D | MipsSEISelLowering.cpp | 419 SDValue Tmp = DAG.getNode(MipsISD::MTC1_D64, DL, MVT::f64, Op->getOperand(0)); local 420 return DAG.getNode(MipsISD::FSELECT, DL, ResTy, Tmp, Op->getOperand(1), 3531 Register Tmp = RegInfo.createVirtualRegister(&Mips::GPR64RegClass); local 3532 BuildMI(*BB, MI, DL, TII->get(Mips::SUBREG_TO_REG), Tmp) 3536 Rs = Tmp; 3588 Register Tmp = RegInfo.createVirtualRegister(&Mips::GPR32RegClass); local 3589 BuildMI(*BB, MI, DL, TII->get(Mips::COPY), Tmp).addReg(Rt, 0, Mips::sub_32); 3590 Rt = Tmp;
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/freebsd-13-stable/contrib/llvm-project/llvm/lib/MC/ |
H A D | MCDwarf.cpp | 676 SmallString<256> Tmp; local 677 raw_svector_ostream OS(Tmp); 1958 SmallString<256> Tmp; local 1959 raw_svector_ostream OS(Tmp);
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/freebsd-13-stable/contrib/llvm-project/llvm/lib/Target/X86/AsmParser/ |
H A D | X86AsmParser.cpp | 3570 SmallString<16> Tmp; local 3571 Tmp += Base; 3572 Tmp += ' '; 3573 Op.setTokenValue(Tmp); 3611 Tmp.back() = Suffixes[I]; 3793 SmallString<16> Tmp; local 3794 Tmp += Base; 3795 Tmp += (is64BitMode()) 3798 Op.setTokenValue(Tmp);
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/freebsd-13-stable/contrib/llvm-project/clang/lib/AST/ |
H A D | FormatString.cpp | 106 const char *Tmp = Beg; local 110 Tmp, 0, true);
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/freebsd-13-stable/contrib/llvm-project/llvm/lib/ExecutionEngine/Interpreter/ |
H A D | Execution.cpp | 1613 APInt Tmp; 1614 Tmp = Tmp.zext(SrcBitSize); 1615 Tmp = TempSrc.AggregateVal[SrcElt++].IntVal; 1616 Tmp = Tmp.zext(DstBitSize); 1617 Tmp <<= ShiftAmt; 1619 Elt.IntVal |= Tmp;
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/freebsd-13-stable/contrib/llvm-project/llvm/tools/llvm-diff/ |
H A D | DifferenceEngine.cpp | 723 SmallString<32> Tmp; local 727 .toStringRef(Tmp));
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/freebsd-13-stable/contrib/llvm-project/llvm/utils/TableGen/ |
H A D | AsmMatcherEmitter.cpp | 242 RegisterSet Tmp; 243 std::insert_iterator<RegisterSet> II(Tmp, Tmp.begin()); 248 return !Tmp.empty(); 1250 RegisterSet Tmp; 1251 std::swap(Tmp, ContainingSet); 1254 std::set_intersection(Tmp.begin(), Tmp.end(), RS.begin(), RS.end(), II,
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/freebsd-13-stable/contrib/llvm-project/llvm/lib/Target/ARM/MCTargetDesc/ |
H A D | ARMAsmBackend.cpp | 331 SmallString<256> Tmp; local 332 raw_svector_ostream OS(Tmp);
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/freebsd-13-stable/contrib/llvm-project/llvm/include/llvm/Support/ |
H A D | Error.h | 310 std::unique_ptr<ErrorInfoBase> Tmp(getPtr()); 313 return Tmp;
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/freebsd-13-stable/contrib/llvm-project/clang/lib/CodeGen/ |
H A D | TargetInfo.cpp | 4028 Address Tmp = CGF.CreateMemTemp(Ty); 4029 Tmp = CGF.Builder.CreateElementBitCast(Tmp, ST); 4047 CGF.Builder.CreateStore(V, CGF.Builder.CreateStructGEP(Tmp, 0)); 4053 CGF.Builder.CreateStore(V, CGF.Builder.CreateStructGEP(Tmp, 1)); 4055 RegAddr = CGF.Builder.CreateElementBitCast(Tmp, LTy); 4070 Address Tmp = CGF.CreateMemTemp(Ty); 4071 CGF.Builder.CreateMemCpy(Tmp, RegAddr, TySize, false); 4072 RegAddr = Tmp; 4096 Address Tmp [all...] |
H A D | CGCall.cpp | 1264 Address Tmp = CreateTempAllocaForCoercion(CGF, Ty, Src.getAlignment()); local 1265 CGF.Builder.CreateMemCpy(Tmp.getPointer(), Tmp.getAlignment().getAsAlign(), 1268 return CGF.Builder.CreateLoad(Tmp); 1347 Address Tmp = CreateTempAllocaForCoercion(CGF, SrcTy, Dst.getAlignment()); local 1348 CGF.Builder.CreateStore(Src, Tmp); 1350 Tmp.getPointer(), Tmp.getAlignment().getAsAlign(),
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/freebsd-13-stable/contrib/llvm-project/llvm/include/llvm/Demangle/ |
H A D | ItaniumDemangle.h | 2196 auto* Tmp = static_cast<T*>(std::malloc(NewCap * sizeof(T))); local 2197 if (Tmp == nullptr) 2199 std::copy(First, Last, Tmp); 2200 First = Tmp; 3399 const char *Tmp = First; local 3406 return StringView(Tmp, First); 4048 StringView Tmp = parseNumber(true); local 4049 if (!Tmp.empty() && consumeIf('E')) 4050 return make<IntegerLiteral>(Lit, Tmp);
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/freebsd-13-stable/contrib/llvm-project/llvm/lib/Transforms/Instrumentation/ |
H A D | GCOVProfiling.cpp | 805 char Tmp[4]; 814 std::reverse_copy(Options.Version, Options.Version + 4, Tmp); 815 out.write(Tmp, 4);
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/freebsd-13-stable/contrib/llvm-project/llvm/lib/Target/X86/ |
H A D | X86InstructionSelector.cpp | 1378 Register Tmp = MRI.createGenericVirtualRegister(DstTy); local 1379 MRI.setRegBank(Tmp, RegBank); 1382 TII.get(TargetOpcode::G_INSERT), Tmp) 1387 DefReg = Tmp;
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/freebsd-13-stable/contrib/llvm-project/llvm/lib/Target/AArch64/ |
H A D | AArch64TargetTransformInfo.cpp | 77 APInt Tmp = ImmVal.ashr(ShiftVal).sextOrTrunc(64); local 78 int64_t Val = Tmp.getSExtValue();
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/freebsd-13-stable/contrib/llvm-project/llvm/lib/Target/X86/MCTargetDesc/ |
H A D | X86AsmBackend.cpp | 835 SmallString<256> Tmp; local 836 raw_svector_ostream OS(Tmp);
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/freebsd-13-stable/contrib/llvm-project/llvm/lib/Target/PowerPC/ |
H A D | PPCISelDAGToDAG.cpp | 4199 SDValue Tmp = local 4201 CurDAG->SelectNodeTo(N, PPC::XORI, MVT::i32, Tmp, getI32Imm(1, dl)); 5032 SDNode *Tmp = local 5035 CurDAG->SelectNodeTo(N, PPC::SUBFE, MVT::i32, SDValue(Tmp, 0), 5036 N->getOperand(0), SDValue(Tmp, 1)); 5314 SDNode *Tmp = CurDAG->getMachineNode( local 5321 isPPC64 ? PPC::LDtocL : PPC::LWZtocL, dl, VT, GA, SDValue(Tmp, 0)); 5330 SDValue(Tmp, 0), GA)); 5380 SDNode *Tmp = CurDAG->getMachineNode(Opc1, dl, VT, EltVal); local 5381 SDValue TmpVal = SDValue(Tmp, [all...] |
/freebsd-13-stable/contrib/llvm-project/llvm/lib/Target/AMDGPU/ |
H A D | SIInstrInfo.cpp | 702 Register Tmp = RS.scavengeRegister(&AMDGPU::VGPR_32RegClass, 0); local 703 if (!Tmp) 705 RS.setRegUsed(Tmp); 713 Tmp = Tmp2; 714 RS.setRegUsed(Tmp); 716 copyPhysReg(MBB, MI, DL, Tmp, SrcReg, KillSrc); 718 .addReg(Tmp, RegState::Kill); 1289 Register Tmp = MRI.createVirtualRegister(&AMDGPU::VGPR_32RegClass); local 1290 MIB.addReg(Tmp, RegState::Define); 1414 Register Tmp local 1788 auto Tmp = MRI.createVirtualRegister(&AMDGPU::VGPR_32RegClass); local [all...] |