/freebsd-13-stable/contrib/llvm-project/llvm/lib/Target/XCore/ |
H A D | XCoreFrameLowering.cpp | 62 const DebugLoc &dl, const TargetInstrInfo &TII, 66 BuildMI(MBB, MBBI, dl, TII.get(TargetOpcode::CFI_INSTRUCTION)) 72 const DebugLoc &dl, const TargetInstrInfo &TII, 77 BuildMI(MBB, MBBI, dl, TII.get(TargetOpcode::CFI_INSTRUCTION)) 83 const TargetInstrInfo &TII, unsigned DRegNum, 88 BuildMI(MBB, MBBI, dl, TII.get(TargetOpcode::CFI_INSTRUCTION)) 100 const TargetInstrInfo &TII, int OffsetFromTop, 107 BuildMI(MBB, MBBI, dl, TII.get(Opcode)).addImm(OpImm); 110 EmitDefCfaOffset(MBB, MBBI, dl, TII, Adjusted*4); 123 const TargetInstrInfo &TII, in 60 EmitDefCfaRegister(MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI, const DebugLoc &dl, const TargetInstrInfo &TII, MachineFunction &MF, unsigned DRegNum) argument 70 EmitDefCfaOffset(MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI, const DebugLoc &dl, const TargetInstrInfo &TII, int Offset) argument 81 EmitCfiOffset(MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI, const DebugLoc &dl, const TargetInstrInfo &TII, unsigned DRegNum, int Offset) argument 98 IfNeededExtSP(MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI, const DebugLoc &dl, const TargetInstrInfo &TII, int OffsetFromTop, int &Adjusted, int FrameSize, bool emitFrameMoves) argument 121 IfNeededLDAWSP(MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI, const DebugLoc &dl, const TargetInstrInfo &TII, int OffsetFromTop, int &RemainingAdj) argument 190 RestoreSpillList(MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI, const DebugLoc &dl, const TargetInstrInfo &TII, int &RemainingAdj, SmallVectorImpl<StackSlotInfo> &SpillList) argument 230 const XCoreInstrInfo &TII = *MF.getSubtarget<XCoreSubtarget>().getInstrInfo(); local 347 const XCoreInstrInfo &TII = *MF.getSubtarget<XCoreSubtarget>().getInstrInfo(); local 422 const TargetInstrInfo &TII = *MF->getSubtarget().getInstrInfo(); local 452 const TargetInstrInfo &TII = *MF->getSubtarget().getInstrInfo(); local 483 const XCoreInstrInfo &TII = *MF.getSubtarget<XCoreSubtarget>().getInstrInfo(); local [all...] |
/freebsd-13-stable/contrib/llvm-project/llvm/lib/Target/PowerPC/ |
H A D | PPCTLSDynamicCall.cpp | 45 const PPCInstrInfo *TII; member in struct:__anon4281::PPCTLSDynamicCall 113 BuildMI(MBB, I, DL, TII->get(PPC::ADJCALLSTACKDOWN)).addImm(0) 117 MachineInstr *Addi = BuildMI(MBB, I, DL, TII->get(Opc1), GPR3) 126 MachineInstr *Call = (BuildMI(MBB, I, DL, TII->get(Opc2), GPR3) 131 BuildMI(MBB, I, DL, TII->get(PPC::ADJCALLSTACKUP)).addImm(0).addImm(0); 133 BuildMI(MBB, I, DL, TII->get(TargetOpcode::COPY), OutReg) 154 TII = MF.getSubtarget<PPCSubtarget>().getInstrInfo();
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H A D | PPCBranchSelector.cpp | 119 const PPCInstrInfo *TII = local 142 unsigned MINumBytes = TII->getInstSizeInBytes(MI); 145 if (TII->isPrefixed(MI.getOpcode())) { 295 const PPCInstrInfo *TII = local 346 MBBStartOffset += TII->getInstSizeInBytes(*I); 373 BuildMI(MBB, I, dl, TII->get(PPC::BCC)) 377 BuildMI(MBB, I, dl, TII->get(PPC::BCn)).addReg(CRBit).addImm(2); 380 BuildMI(MBB, I, dl, TII->get(PPC::BC)).addReg(CRBit).addImm(2); 382 BuildMI(MBB, I, dl, TII->get(PPC::BDZ)).addImm(2); 384 BuildMI(MBB, I, dl, TII [all...] |
/freebsd-13-stable/contrib/llvm-project/llvm/lib/CodeGen/ |
H A D | TargetSchedule.cpp | 66 TII = TSInfo->getInstrInfo(); 111 return (UOps >= 0) ? UOps : TII->getNumMicroOps(&InstrItins, *MI); 189 return TII->defaultDefLatency(SchedModel, *DefMI); 194 OperLatency = TII->getOperandLatency(&InstrItins, *DefMI, DefOperIdx, 205 unsigned InstrLatency = TII->getInstrLatency(&InstrItins, *DefMI); 208 // Rather than directly querying InstrItins stage latency, we call a TII 211 // special cases without TII hooks. 213 std::max(InstrLatency, TII->defaultDefLatency(SchedModel, *DefMI)); 252 return DefMI->isTransient() ? 0 : TII->defaultDefLatency(SchedModel, *DefMI); 262 unsigned SCIdx = TII [all...] |
H A D | MachineLoopUtils.cpp | 30 const TargetInstrInfo *TII) { 110 if (TII->removeBranch(*Preheader) > 0) 111 TII->insertBranch(*Preheader, NewBB, nullptr, {}, DL); 112 TII->removeBranch(*NewBB); 113 TII->insertBranch(*NewBB, Loop, nullptr, {}, DL); 121 bool CanAnalyzeBr = !TII->analyzeBranch(*Loop, TBB, FBB, Cond); 124 TII->removeBranch(*Loop); 125 TII->insertBranch(*Loop, TBB == Exit ? NewBB : TBB, 127 if (TII->removeBranch(*NewBB) > 0) 128 TII 27 PeelSingleBlockLoop(LoopPeelDirection Direction, MachineBasicBlock *Loop, MachineRegisterInfo &MRI, const TargetInstrInfo *TII) argument [all...] |
H A D | BranchRelaxation.cpp | 86 const TargetInstrInfo *TII; member in class:__anon3441::BranchRelaxation 168 Size += TII->getInstSizeInBytes(MI); 186 Offset += TII->getInstSizeInBytes(*I); 237 TII->insertUnconditionalBranch(*OrigBB, NewBB, DebugLoc()); 280 if (TII->isBranchOffsetInRange(MI.getOpcode(), DestOffset - BrOffset)) 306 TII->insertUnconditionalBranch(*MBB, DestBB, DL, &NewBrSize); 314 TII->insertBranch(*MBB, TBB, FBB, Cond, DL, &NewBrSize); 320 TII->removeBranch(*MBB, &RemovedSize); 334 bool Fail = TII->analyzeBranch(*MBB, TBB, FBB, Cond); 346 bool ReversedCond = !TII [all...] |
/freebsd-13-stable/contrib/llvm-project/llvm/lib/Target/ARM/ |
H A D | Thumb1FrameLowering.cpp | 69 const TargetInstrInfo &TII, const DebugLoc &dl, 84 BuildMI(MBB, MBBI, dl, TII.get(ARM::t2MOVi32imm), ScratchReg) 90 BuildMI(MBB, MBBI, dl, TII.get(ARM::tADDhirr), ARM::SP) 99 emitThumbRegPlusImmediate(MBB, MBBI, dl, ARM::SP, ARM::SP, NumBytes, TII, 106 const TargetInstrInfo &TII, const DebugLoc &dl, 109 emitThumbRegPlusImmediate(MBB, MBBI, dl, ARM::SP, ARM::SP, NumBytes, TII, 117 const Thumb1InstrInfo &TII = local 127 unsigned Amount = TII.getFrameSize(Old); 137 emitCallSPUpdate(MBB, I, TII, dl, *RegInfo, -Amount); 140 emitCallSPUpdate(MBB, I, TII, d 67 emitPrologueEpilogueSPUpdate(MachineBasicBlock &MBB, MachineBasicBlock::iterator &MBBI, const TargetInstrInfo &TII, const DebugLoc &dl, const ThumbRegisterInfo &MRI, int NumBytes, unsigned ScratchReg, unsigned MIFlags) argument 104 emitCallSPUpdate(MachineBasicBlock &MBB, MachineBasicBlock::iterator &MBBI, const TargetInstrInfo &TII, const DebugLoc &dl, const ThumbRegisterInfo &MRI, int NumBytes, unsigned MIFlags = MachineInstr::NoFlags) argument 156 const Thumb1InstrInfo &TII = local 480 const Thumb1InstrInfo &TII = local 607 const TargetInstrInfo &TII = *STI.getInstrInfo(); local 816 const TargetInstrInfo &TII = *STI.getInstrInfo(); local 938 const TargetInstrInfo &TII = *STI.getInstrInfo(); local [all...] |
H A D | ThumbRegisterInfo.cpp | 69 const TargetInstrInfo &TII = *STI.getInstrInfo(); local 75 BuildMI(MBB, MBBI, dl, TII.get(ARM::tLDRpci)) 88 const TargetInstrInfo &TII = *MF.getSubtarget().getInstrInfo(); local 94 BuildMI(MBB, MBBI, dl, TII.get(ARM::t2LDRpci)) 126 bool CanChangeCC, const TargetInstrInfo &TII, 148 BuildMI(MBB, MBBI, dl, TII.get(ARM::tMOVi8), LdReg) 153 BuildMI(MBB, MBBI, dl, TII.get(ARM::tMOVi8), LdReg) 157 BuildMI(MBB, MBBI, dl, TII.get(ARM::tRSB), LdReg) 162 BuildMI(MBB, MBBI, dl, TII.get(ARM::t2MOVi32imm), LdReg) 171 MachineInstrBuilder MIB = BuildMI(MBB, MBBI, dl, TII 123 emitThumbRegPlusImmInReg( MachineBasicBlock &MBB, MachineBasicBlock::iterator &MBBI, const DebugLoc &dl, Register DestReg, Register BaseReg, int NumBytes, bool CanChangeCC, const TargetInstrInfo &TII, const ARMBaseRegisterInfo &MRI, unsigned MIFlags = MachineInstr::NoFlags) argument 185 emitThumbRegPlusImmediate(MachineBasicBlock &MBB, MachineBasicBlock::iterator &MBBI, const DebugLoc &dl, Register DestReg, Register BaseReg, int NumBytes, const TargetInstrInfo &TII, const ARMBaseRegisterInfo &MRI, unsigned MIFlags) argument [all...] |
/freebsd-13-stable/contrib/llvm-project/llvm/lib/Target/Mips/ |
H A D | MipsExpandPseudo.cpp | 38 const MipsInstrInfo *TII; member in class:__anon4219::MipsExpandPseudo 145 BuildMI(loop1MBB, DL, TII->get(LL), Scratch).addReg(Ptr).addImm(0); 146 BuildMI(loop1MBB, DL, TII->get(Mips::AND), Scratch2) 149 BuildMI(loop1MBB, DL, TII->get(BNE)) 157 BuildMI(loop2MBB, DL, TII->get(Mips::AND), Scratch) 160 BuildMI(loop2MBB, DL, TII->get(Mips::OR), Scratch) 163 BuildMI(loop2MBB, DL, TII->get(SC), Scratch) 167 BuildMI(loop2MBB, DL, TII->get(BEQ)) 175 BuildMI(sinkMBB, DL, TII->get(Mips::SRLV), Dest) 179 BuildMI(sinkMBB, DL, TII [all...] |
H A D | MipsMachineFunction.cpp | 69 const TargetInstrInfo &TII = *MF.getSubtarget().getInstrInfo(); local 87 BuildMI(MBB, I, DL, TII.get(Mips::LUi64), V0) 89 BuildMI(MBB, I, DL, TII.get(Mips::DADDu), V1).addReg(V0) 91 BuildMI(MBB, I, DL, TII.get(Mips::DADDiu), GlobalBaseReg).addReg(V1) 101 BuildMI(MBB, I, DL, TII.get(Mips::LUi), V0) 103 BuildMI(MBB, I, DL, TII.get(Mips::ADDiu), GlobalBaseReg).addReg(V0) 116 BuildMI(MBB, I, DL, TII.get(Mips::LUi), V0) 118 BuildMI(MBB, I, DL, TII.get(Mips::ADDu), V1).addReg(V0).addReg(Mips::T9); 119 BuildMI(MBB, I, DL, TII.get(Mips::ADDiu), GlobalBaseReg).addReg(V1) 145 BuildMI(MBB, I, DL, TII [all...] |
/freebsd-13-stable/contrib/llvm-project/llvm/lib/Target/AMDGPU/ |
H A D | SIOptimizeExecMasking.cpp | 181 static bool removeTerminatorBit(const SIInstrInfo &TII, MachineInstr &MI) { argument 185 MI.setDesc(TII.get(AMDGPU::COPY)); 191 MI.setDesc(TII.get(AMDGPU::S_XOR_B64)); 197 MI.setDesc(TII.get(AMDGPU::S_XOR_B32)); 203 MI.setDesc(TII.get(AMDGPU::S_OR_B32)); 209 MI.setDesc(TII.get(AMDGPU::S_ANDN2_B64)); 215 MI.setDesc(TII.get(AMDGPU::S_ANDN2_B32)); 224 const SIInstrInfo &TII, 231 if (removeTerminatorBit(TII, *I)) 239 const SIInstrInfo &TII, 223 fixTerminators( const SIInstrInfo &TII, MachineBasicBlock &MBB) argument 238 findExecCopy( const SIInstrInfo &TII, const GCNSubtarget &ST, MachineBasicBlock &MBB, MachineBasicBlock::reverse_iterator I, unsigned CopyToExec) argument 274 const SIInstrInfo *TII = ST.getInstrInfo(); local [all...] |
H A D | SIFrameLowering.cpp | 135 const SIInstrInfo *TII, Register SpillReg, 147 BuildMI(MBB, I, DebugLoc(), TII->get(AMDGPU::BUFFER_STORE_DWORD_OFFSET)) 164 BuildMI(MBB, I, DebugLoc(), TII->get(AMDGPU::V_MOV_B32_e32), OffsetReg) 167 BuildMI(MBB, I, DebugLoc(), TII->get(AMDGPU::BUFFER_STORE_DWORD_OFFEN)) 183 const SIInstrInfo *TII, Register SpillReg, 195 TII->get(AMDGPU::BUFFER_LOAD_DWORD_OFFSET), SpillReg) 211 BuildMI(MBB, I, DebugLoc(), TII->get(AMDGPU::V_MOV_B32_e32), OffsetReg) 215 TII->get(AMDGPU::BUFFER_LOAD_DWORD_OFFEN), SpillReg) 233 const SIInstrInfo *TII = ST.getInstrInfo(); local 234 const SIRegisterInfo *TRI = &TII 133 buildPrologSpill(LivePhysRegs &LiveRegs, MachineBasicBlock &MBB, MachineBasicBlock::iterator I, const SIInstrInfo *TII, Register SpillReg, Register ScratchRsrcReg, Register SPReg, int FI) argument 181 buildEpilogReload(LivePhysRegs &LiveRegs, MachineBasicBlock &MBB, MachineBasicBlock::iterator I, const SIInstrInfo *TII, Register SpillReg, Register ScratchRsrcReg, Register SPReg, int FI) argument 310 const SIInstrInfo *TII = ST.getInstrInfo(); local 374 const SIInstrInfo *TII = ST.getInstrInfo(); local 485 const SIInstrInfo *TII = ST.getInstrInfo(); local 647 const SIInstrInfo *TII = ST.getInstrInfo(); local 693 const SIInstrInfo *TII = ST.getInstrInfo(); local 934 const SIInstrInfo *TII = ST.getInstrInfo(); local 1241 const SIInstrInfo *TII = ST.getInstrInfo(); local [all...] |
H A D | SIInsertSkips.cpp | 56 const SIInstrInfo *TII = nullptr; member in class:__anon3975::SIInsertSkips 141 if (TII->hasUnwantedEffectsWhenEXECEmpty(*I)) 145 if (TII->isSMRD(*I) || TII->isVMEM(*I) || TII->isFLAT(*I) || 169 const SIInstrInfo *TII) { 171 BuildMI(MBB, I, DL, TII->get(AMDGPU::EXP_DONE)) 180 BuildMI(MBB, I, DL, TII->get(AMDGPU::S_ENDPGM)).addImm(0); 191 generatePsEndPgm(*EarlyExitBlock, EarlyExitBlock->end(), DL, TII); 218 generatePsEndPgm(MBB, I, DL, TII); 167 generatePsEndPgm(MachineBasicBlock &MBB, MachineBasicBlock::iterator I, DebugLoc DL, const SIInstrInfo *TII) argument [all...] |
H A D | SIInsertWaitcnts.cpp | 268 RegInterval getRegInterval(const MachineInstr *MI, const SIInstrInfo *TII, 279 void updateByEvent(const SIInstrInfo *TII, const SIRegisterInfo *TRI, 357 void setExpScore(const MachineInstr *MI, const SIInstrInfo *TII, 382 const SIInstrInfo *TII = nullptr; 474 const SIInstrInfo *TII, 506 const TargetRegisterClass *RC = TII->getOpRegClass(*MI, OpNo); 514 const SIInstrInfo *TII, 518 RegInterval Interval = getRegInterval(MI, TII, MRI, TRI, OpNo); 525 void WaitcntBrackets::updateByEvent(const SIInstrInfo *TII, 542 if (TII [all...] |
/freebsd-13-stable/contrib/llvm-project/llvm/lib/Target/SystemZ/ |
H A D | SystemZPostRewrite.cpp | 43 const SystemZInstrInfo *TII; member in class:__anon4339::SystemZPostRewrite 95 MBBI->setDesc(TII->get(LowOpcode)); 97 MBBI->setDesc(TII->get(HighOpcode)); 123 TII->get(SystemZ::COPY), DestReg) 130 TII->get(SystemZ::COPY), DestReg) 140 TII->commuteInstruction(*MBBI, false, 1, 2); 146 MBBI->setDesc(TII->get(LowOpcode)); 148 MBBI->setDesc(TII->get(HighOpcode)); 171 LivePhysRegs LiveRegs(TII->getRegisterInfo()); 193 BuildMI(&MBB, DL, TII [all...] |
H A D | SystemZLongBranch.cpp | 164 const SystemZInstrInfo *TII = nullptr; member in class:__anon4338::SystemZLongBranch 215 Terminator.Size = TII->getInstSizeInBytes(MI); 260 TII->getBranchInfo(MI).getMBBTarget()->getNumber(); 290 Block.Size += TII->getInstSizeInBytes(*MI); 358 BuildMI(*MBB, MI, DL, TII->get(AddOpcode)) 362 MachineInstr *BRCL = BuildMI(*MBB, MI, DL, TII->get(SystemZ::BRCL)) 367 BRCL->addRegisterKilled(SystemZ::CC, &TII->getRegisterInfo()); 377 BuildMI(*MBB, MI, DL, TII->get(CompareOpcode)) 380 MachineInstr *BRCL = BuildMI(*MBB, MI, DL, TII->get(SystemZ::BRCL)) 385 BRCL->addRegisterKilled(SystemZ::CC, &TII [all...] |
/freebsd-13-stable/contrib/llvm-project/llvm/lib/Target/ARC/ |
H A D | ARCFrameLowering.cpp | 46 const ARCInstrInfo &TII, DebugLoc dl, 72 BuildMI(MBB, MBBI, dl, TII.get(AdjOp), StackPtr) 122 const ARCInstrInfo *TII = MF.getSubtarget<ARCSubtarget>().getInstrInfo(); local 142 BuildMI(MBB, MBBI, dl, TII->get(Opc), ARC::SP) 148 BuildMI(MBB, MBBI, dl, TII->get(ARC::ST_AW_rs9)) 159 BuildMI(MBB, MBBI, dl, TII->get(ARC::PUSH_S_BLINK)); 160 BuildMI(MBB, MBBI, dl, TII->get(ARC::SUB_rru6)) 164 BuildMI(MBB, MBBI, dl, TII->get(ARC::BL)) 173 BuildMI(MBB, MBBI, dl, TII->get(ARC::PUSH_S_BLINK)); 187 TII 44 generateStackAdjustment(MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI, const ARCInstrInfo &TII, DebugLoc dl, int Amount, int StackPtr) argument 243 const ARCInstrInfo *TII = MF.getSubtarget<ARCSubtarget>().getInstrInfo(); local 450 emitRegUpdate(MachineBasicBlock &MBB, MachineBasicBlock::iterator &MBBI, DebugLoc dl, unsigned Reg, int NumBytes, bool IsAdd, const ARCInstrInfo *TII) argument 471 const ARCInstrInfo *TII = MF.getSubtarget<ARCSubtarget>().getInstrInfo(); local [all...] |
H A D | ARCBranchFinalize.cpp | 55 const ARCInstrInfo *TII{nullptr}; 119 TII->get(getBRccForPseudo(MI))) 134 TII->get(getCmpForPseudo(MI))) 137 BuildMI(*MI->getParent(), MI, MI->getDebugLoc(), TII->get(ARC::Bcc)) 149 TII = MF.getSubtarget<ARCSubtarget>().getInstrInfo(); 157 unsigned Size = TII->getInstSizeInBytes(MI);
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/freebsd-13-stable/contrib/llvm-project/llvm/lib/Target/MSP430/ |
H A D | MSP430BranchSelector.cpp | 43 const MSP430InstrInfo *TII; member in class:__anon4189::MSP430BSel 99 TotalSize += TII->getInstSizeInBytes(MI); 121 MBBStartOffset += TII->getInstSizeInBytes(*MI); 181 int InstrSizeDiff = -TII->getInstSizeInBytes(OldBranch); 195 TII->reverseBranchCondition(Cond); 196 MI = BuildMI(*MBB, MI, dl, TII->get(MSP430::JCC)) 199 InstrSizeDiff += TII->getInstSizeInBytes(*MI); 204 MI = BuildMI(*MBB, MI, dl, TII->get(MSP430::Bi)).addMBB(DestBB); 205 InstrSizeDiff += TII->getInstSizeInBytes(*MI); 226 TII [all...] |
/freebsd-13-stable/contrib/llvm-project/llvm/lib/Target/X86/ |
H A D | X86IndirectThunks.cpp | 94 const TargetInstrInfo *TII = MF.getSubtarget<X86Subtarget>().getInstrInfo(); local 95 BuildMI(&MF.front(), DebugLoc(), TII->get(X86::LFENCE)); 96 BuildMI(&MF.front(), DebugLoc(), TII->get(X86::JMP64r)).addReg(X86::R11); 202 const TargetInstrInfo *TII = MF.getSubtarget<X86Subtarget>().getInstrInfo(); local 219 BuildMI(Entry, DebugLoc(), TII->get(CallOpc)).addSym(TargetSym); 234 BuildMI(CaptureSpec, DebugLoc(), TII->get(X86::PAUSE)); 235 BuildMI(CaptureSpec, DebugLoc(), TII->get(X86::LFENCE)); 236 BuildMI(CaptureSpec, DebugLoc(), TII->get(X86::JMP_1)).addMBB(CaptureSpec); 247 addRegOffset(BuildMI(CallTarget, DebugLoc(), TII->get(MovOpc)), SPReg, false, 252 BuildMI(CallTarget, DebugLoc(), TII [all...] |
H A D | X86ExpandPseudo.cpp | 45 const X86InstrInfo *TII = nullptr; member in class:__anon4426::X86ExpandPseudo 92 BuildMI(*MBB, MBBI, DL, TII->get(X86::LEA64r), X86::R11) 99 BuildMI(*MBB, MBBI, DL, TII->get(X86::CMP64rr)) 113 BuildMI(*MBB, MBBI, DL, TII->get(X86::JCC_1)).addMBB(ThenMBB).addImm(CC); 128 BuildMI(*MBB, MBBI, DL, TII->get(X86::TAILJMPd64)) 170 BuildMI(P.first, DL, TII->get(X86::TAILJMPd64)) 245 MachineInstrBuilder MIB = BuildMI(MBB, MBBI, DL, TII->get(Op)); 262 MachineInstrBuilder MIB = BuildMI(MBB, MBBI, DL, TII->get(Op)); 268 TII->get(IsWin64 ? X86::TAILJMPr64_REX : X86::TAILJMPr64)) 272 BuildMI(MBB, MBBI, DL, TII [all...] |
/freebsd-13-stable/contrib/llvm-project/llvm/lib/Target/AArch64/ |
H A D | AArch64ExpandPseudoInsts.cpp | 52 const AArch64InstrInfo *TII; member in class:__anon3846::AArch64ExpandPseudo 142 MIBS.push_back(BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(I->Opcode)) 152 MIBS.push_back(BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(I->Opcode)) 163 MIBS.push_back(BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(I->Opcode)) 210 BuildMI(LoadCmpBB, DL, TII->get(AArch64::MOVZWi), StatusReg) 212 BuildMI(LoadCmpBB, DL, TII->get(LdarOp), Dest.getReg()) 214 BuildMI(LoadCmpBB, DL, TII->get(CmpOp), ZeroReg) 218 BuildMI(LoadCmpBB, DL, TII->get(AArch64::Bcc)) 228 BuildMI(StoreBB, DL, TII->get(StlrOp), StatusReg) 231 BuildMI(StoreBB, DL, TII [all...] |
H A D | AArch64CompressJumpTables.cpp | 36 const TargetInstrInfo *TII; member in class:__anon3840::AArch64CompressJumpTables 70 Size += TII->getInstSizeInBytes(MI); 130 MI.setDesc(TII->get(AArch64::JumpTableDest8)); 135 MI.setDesc(TII->get(AArch64::JumpTableDest16)); 149 TII = ST.getInstrInfo(); 160 Offset += TII->getInstSizeInBytes(MI);
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/freebsd-13-stable/contrib/llvm-project/llvm/lib/Target/Sparc/ |
H A D | SparcFrameLowering.cpp | 48 const SparcInstrInfo &TII = local 52 BuildMI(MBB, MBBI, dl, TII.get(ADDri), SP::O6) 64 BuildMI(MBB, MBBI, dl, TII.get(SP::SETHIi), SP::G1) 66 BuildMI(MBB, MBBI, dl, TII.get(SP::ORri), SP::G1) 68 BuildMI(MBB, MBBI, dl, TII.get(ADDrr), SP::O6) 77 BuildMI(MBB, MBBI, dl, TII.get(SP::SETHIi), SP::G1) 79 BuildMI(MBB, MBBI, dl, TII.get(SP::XORri), SP::G1) 81 BuildMI(MBB, MBBI, dl, TII.get(ADDrr), SP::O6) 92 const SparcInstrInfo &TII = local 161 BuildMI(MBB, MBBI, dl, TII 223 const SparcInstrInfo &TII = local [all...] |
/freebsd-13-stable/contrib/llvm-project/llvm/lib/Target/WebAssembly/ |
H A D | WebAssemblyLateEHPrepare.cpp | 151 const auto &TII = *MF.getSubtarget<WebAssemblySubtarget>().getInstrInfo(); local 161 TII.get(WebAssembly::CATCH), DstReg); 169 const auto &TII = *MF.getSubtarget<WebAssemblySubtarget>().getInstrInfo(); local 182 BuildMI(MBB, TI, TI->getDebugLoc(), TII.get(WebAssembly::BR)) 197 BuildMI(MBB, TI, TI->getDebugLoc(), TII.get(WebAssembly::RETHROW)) 260 const auto &TII = *MF.getSubtarget<WebAssemblySubtarget>().getInstrInfo(); local 333 BuildMI(EHPad, DL, TII.get(WebAssembly::BR_ON_EXN)) 337 BuildMI(EHPad, DL, TII.get(WebAssembly::BR)).addMBB(ElseMBB); 369 BuildMI(ElseMBB, DL, TII.get(WebAssembly::CONST_I32), Reg).addImm(0); 370 BuildMI(ElseMBB, DL, TII [all...] |