Searched refs:TII (Results 276 - 300 of 403) sorted by relevance

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/freebsd-13-stable/contrib/llvm-project/llvm/lib/CodeGen/
H A DSplitKit.h102 const TargetInstrInfo &TII; member in class:llvm::SplitAnalysis
265 const TargetInstrInfo &TII; member in class:llvm::SplitEditor
H A DUnreachableBlockElim.cpp193 const TargetInstrInfo *TII = F.getSubtarget().getInstrInfo(); local
195 TII->get(TargetOpcode::COPY), OutputReg)
H A DDFAPacketizer.cpp150 : MF(mf), TII(mf.getSubtarget().getInstrInfo()), AA(aa) {
151 ResourceTracker = TII->CreateTargetScheduleState(MF.getSubtarget());
H A DPHIElimination.cpp293 const TargetInstrInfo *TII = MF.getSubtarget().getInstrInfo(); local
298 TII->get(TargetOpcode::IMPLICIT_DEF), DestReg);
315 PHICopy = TII->createPHIDestinationCopy(MBB, AfterPHIsIt, MPhi->getDebugLoc(),
436 TII->get(TargetOpcode::IMPLICIT_DEF),
445 TII->createPHISourceCopy(opBlock, InsertPos, MPhi->getDebugLoc(),
H A DMachineCSE.cpp66 const TargetInstrInfo *TII; member in class:__anon3503::MachineCSE
457 if (TII->isAsCheapAsAMove(*MI)) {
542 if (MachineInstr *NewMI = TII->commuteInstruction(*MI)) {
551 (void)TII->commuteInstruction(*MI);
832 TII->duplicate(*CMBB, CMBB->getFirstTerminator(), *MI);
891 TII = MF.getSubtarget().getInstrInfo();
897 LookAheadLimit = TII->getMachineCSELookAheadLimit();
H A DTargetInstrInfo.cpp472 const TargetInstrInfo &TII) {
503 MF.CreateMachineInstr(TII.get(MI.getOpcode()), MI.getDebugLoc(), true);
519 TII.getStackSlotRange(RC, MO.getSubReg(), SpillSize, SpillOffset, MF);
788 const TargetInstrInfo *TII = MF->getSubtarget().getInstrInfo(); local
790 const TargetRegisterClass *RC = Root.getRegClassConstraint(0, TII, TRI);
847 BuildMI(*MF, Prev.getDebugLoc(), TII->get(Opcode), NewVR)
851 BuildMI(*MF, Root.getDebugLoc(), TII->get(Opcode), RegC)
1187 const auto &TII = MF->getSubtarget().getInstrInfo(); local
1198 if (!TII->getMemOperandWithOffset(MI, BaseOp, Offset, OffsetIsScalable,
470 foldPatchpoint(MachineFunction &MF, MachineInstr &MI, ArrayRef<unsigned> Ops, int FrameIndex, const TargetInstrInfo &TII) argument
H A DRenameIndependentSubregs.cpp106 const TargetInstrInfo *TII; member in class:__anon3562::RenameIndependentSubregs
332 const MCInstrDesc &MCDesc = TII->get(TargetOpcode::IMPLICIT_DEF);
387 TII = MF.getSubtarget().getInstrInfo();
H A DShrinkWrap.cpp199 const TargetInstrInfo &TII = *Subtarget.getInstrInfo(); local
200 FrameSetupOpcode = TII.getCallFrameSetupOpcode();
201 FrameDestroyOpcode = TII.getCallFrameDestroyOpcode();
H A DMachineRegisterInfo.cpp123 const TargetInstrInfo *TII = MF->getSubtarget().getInstrInfo(); local
137 NewRC = MI->getRegClassConstraintEffect(OpNo, NewRC, TII,
472 const TargetInstrInfo &TII) {
487 TII.get(TargetOpcode::COPY), LiveIns[i].second)
470 EmitLiveInCopies(MachineBasicBlock *EntryMBB, const TargetRegisterInfo &TRI, const TargetInstrInfo &TII) argument
/freebsd-13-stable/contrib/llvm-project/llvm/lib/Target/Mips/
H A DMipsOptimizePICCall.cpp153 const TargetInstrInfo &TII = *MF.getSubtarget().getInstrInfo(); local
156 BuildMI(*MBB, I, I->getDebugLoc(), TII.get(TargetOpcode::COPY), DstReg)
/freebsd-13-stable/contrib/llvm-project/llvm/lib/Target/AMDGPU/
H A DAMDGPUTargetMachine.cpp286 DAG->addMutation(createLoadClusterDAGMutation(DAG->TII, DAG->TRI));
287 DAG->addMutation(createStoreClusterDAGMutation(DAG->TII, DAG->TRI));
297 DAG->addMutation(createLoadClusterDAGMutation(DAG->TII, DAG->TRI));
298 DAG->addMutation(createStoreClusterDAGMutation(DAG->TII, DAG->TRI));
311 DAG->addMutation(createLoadClusterDAGMutation(DAG->TII, DAG->TRI));
312 DAG->addMutation(createStoreClusterDAGMutation(DAG->TII, DAG->TRI));
595 DAG->addMutation(createLoadClusterDAGMutation(DAG->TII, DAG->TRI));
596 DAG->addMutation(createStoreClusterDAGMutation(DAG->TII, DAG->TRI));
H A DAMDGPUAsmPrinter.cpp577 const SIInstrInfo *TII = STM.getInstrInfo(); local
589 CodeSize += TII->getInstSizeInBytes(MI);
597 const SIInstrInfo &TII,
600 if (!UseOp.isImplicit() || !TII.isFLAT(*UseOp.getParent()))
635 const SIInstrInfo *TII = ST.getInstrInfo(); local
636 const SIRegisterInfo &TRI = TII->getRegisterInfo();
648 (!hasAnyNonFlatUseOfReg(MRI, *TII, AMDGPU::FLAT_SCR) &&
649 !hasAnyNonFlatUseOfReg(MRI, *TII, AMDGPU::FLAT_SCR_LO) &&
650 !hasAnyNonFlatUseOfReg(MRI, *TII, AMDGPU::FLAT_SCR_HI))) {
915 = TII
596 hasAnyNonFlatUseOfReg(const MachineRegisterInfo &MRI, const SIInstrInfo &TII, unsigned Reg) argument
[all...]
H A DAMDGPUMCInstLower.cpp178 const auto *TII = static_cast<const SIInstrInfo*>(ST.getInstrInfo()); local
188 OutMI.setOpcode(TII->pseudoToMCOpcode(AMDGPU::S_SWAPPC_B64));
200 int MCOpcode = TII->pseudoToMCOpcode(Opcode);
/freebsd-13-stable/contrib/llvm-project/llvm/lib/Target/ARM/
H A DARMBaseInstrInfo.h440 const TargetInstrInfo *TII) const;
725 const ARMBaseInstrInfo &TII, unsigned MIFlags = 0);
732 const ARMBaseInstrInfo &TII, unsigned MIFlags = 0);
737 const TargetInstrInfo &TII,
756 const ARMBaseInstrInfo &TII);
760 const ARMBaseInstrInfo &TII,
822 const TargetInstrInfo *TII) {
823 const MCInstrDesc &Desc = TII->get(Opcode);
821 isLegalAddressImm(unsigned Opcode, int Imm, const TargetInstrInfo *TII) argument
/freebsd-13-stable/contrib/llvm-project/llvm/lib/Target/X86/
H A DX86AvoidStoreForwardingBlocks.cpp89 const X86InstrInfo *TII = nullptr; member in class:__anon4412::X86AvoidSFBPass
397 TII->getRegClass(TII->get(NLoadOpcode), 0, TRI, *(MBB->getParent())));
399 BuildMI(*MBB, LoadInst, LoadInst->getDebugLoc(), TII->get(NLoadOpcode),
419 BuildMI(*MBB, StInst, StInst->getDebugLoc(), TII->get(NStoreOpcode))
564 const auto *TRC = TII->getRegClass(TII->get(LoadInst->getOpcode()), 0, TRI,
678 TII = MF.getSubtarget<X86Subtarget>().getInstrInfo();
H A DX86InsertPrefetch.cpp188 const TargetInstrInfo *TII = MF.getSubtarget().getInstrInfo(); local
212 const MCInstrDesc &Desc = TII->get(PFetchInstrID);
H A DX86CmovConversion.cpp116 const TargetInstrInfo *TII = nullptr; member in class:__anon4417::X86CmovConverterPass
171 TII = STI.getInstrInfo();
693 BuildMI(MBB, DL, TII->get(X86::JCC_1)).addMBB(SinkMBB).addImm(CC);
761 bool Unfolded = TII->unfoldMemoryOperand(*MBB->getParent(), MI, TmpReg,
836 MIB = BuildMI(*SinkMBB, SinkInsertionPoint, DL, TII->get(X86::PHI), DestReg)
/freebsd-13-stable/contrib/llvm-project/llvm/lib/Target/Hexagon/
H A DHexagonGenPredicate.cpp107 const HexagonInstrInfo *TII = nullptr; member in class:__anon4128::HexagonGenPredicate
275 BuildMI(B, std::next(DefIt), DL, TII->get(TargetOpcode::COPY), NewPR)
423 MachineInstrBuilder MIB = BuildMI(B, MI, DL, TII->get(NewOpc), NewPR.R);
437 BuildMI(B, MI, DL, TII->get(TargetOpcode::COPY), NewOutR)
500 TII = MF.getSubtarget<HexagonSubtarget>().getInstrInfo();
/freebsd-13-stable/contrib/llvm-project/llvm/lib/CodeGen/SelectionDAG/
H A DSelectionDAGDumper.cpp66 if (const TargetInstrInfo *TII = G->getSubtarget().getInstrInfo())
67 if (getMachineOpcode() < TII->getNumOpcodes())
68 return std::string(TII->getName(getMachineOpcode()));
151 else if (const TargetIntrinsicInfo *TII = G->getTarget().getIntrinsicInfo())
152 return TII->getName(IID);
491 const TargetInstrInfo *TII, LLVMContext &Ctx) {
496 MMO.print(OS, MST, SSNs, Ctx, MFI, TII);
509 /*MFI=*/nullptr, /*TII=*/nullptr, Ctx);
/freebsd-13-stable/contrib/llvm-project/llvm/lib/Target/PowerPC/
H A DPPCReduceCRLogicals.cpp155 const PPCInstrInfo *TII = MF->getSubtarget<PPCSubtarget>().getInstrInfo(); local
221 TII->get(NewBROpcode))
225 TII->get(PPC::B))
238 FirstTerminator->setDesc(TII->get(InvertedOpcode));
379 const PPCInstrInfo *TII = nullptr; member in class:__anon4279::PPCReduceCRLogicals
548 const TargetRegisterInfo *TRI = &TII->getRegisterInfo();
571 TII = MF->getSubtarget<PPCSubtarget>().getInstrInfo();
H A DPPCVSXSwapRemoval.cpp99 const PPCInstrInfo *TII; member in struct:__anon4286::PPCVSXSwapRemoval
222 TII = MF->getSubtarget<PPCSubtarget>().getInstrInfo();
803 TII->get(PPC::XXPERMDI), DstReg)
917 TII->get(PPC::COPY), VSRCTmp1)
925 TII->get(PPC::COPY), DstReg)
951 BuildMI(*MBB, MI, MI->getDebugLoc(), TII->get(TargetOpcode::COPY),
978 dbgs() << format(" %14s ", TII->getName(MI->getOpcode()).str().c_str());
H A DPPCISelLowering.cpp11335 const TargetInstrInfo *TII = Subtarget.getInstrInfo(); local
11412 BuildMI(BB, dl, TII->get(LoadMnemonic), dest)
11415 BuildMI(BB, dl, TII->get(BinOpcode), TmpReg).addReg(incr).addReg(dest);
11420 BuildMI(BB, dl, TII->get(AtomicSize == 1 ? PPC::EXTSB : PPC::EXTSH),
11422 BuildMI(BB, dl, TII->get(CmpOpcode), PPC::CR0)
11425 BuildMI(BB, dl, TII->get(CmpOpcode), PPC::CR0)
11428 BuildMI(BB, dl, TII->get(PPC::BCC))
11434 BuildMI(BB, dl, TII->get(StoreMnemonic))
11436 BuildMI(BB, dl, TII->get(PPC::BCC))
11457 const TargetInstrInfo *TII local
11644 const TargetInstrInfo *TII = Subtarget.getInstrInfo(); local
11786 const TargetInstrInfo *TII = Subtarget.getInstrInfo(); local
11921 const TargetInstrInfo *TII = Subtarget.getInstrInfo(); local
12105 const TargetInstrInfo *TII = Subtarget.getInstrInfo(); local
15633 const PPCInstrInfo *TII = Subtarget.getInstrInfo(); local
[all...]
/freebsd-13-stable/contrib/llvm-project/llvm/lib/Target/AVR/
H A DAVRISelLowering.cpp1406 const TargetInstrInfo &TII = *Subtarget.getInstrInfo(); local
1491 BuildMI(BB, dl, TII.get(AVR::CPIRdK)).addReg(ShiftAmtSrcReg).addImm(0);
1492 BuildMI(BB, dl, TII.get(AVR::BREQk)).addMBB(RemBB);
1499 BuildMI(LoopBB, dl, TII.get(AVR::PHI), ShiftReg)
1504 BuildMI(LoopBB, dl, TII.get(AVR::PHI), ShiftAmtReg)
1510 auto ShiftMI = BuildMI(LoopBB, dl, TII.get(Opc), ShiftReg2).addReg(ShiftReg);
1514 BuildMI(LoopBB, dl, TII.get(AVR::SUBIRdK), ShiftAmtReg2)
1517 BuildMI(LoopBB, dl, TII.get(AVR::BRNEk)).addMBB(LoopBB);
1521 BuildMI(*RemBB, RemBB->begin(), dl, TII.get(AVR::PHI), DstReg)
1545 const TargetInstrInfo &TII local
1585 const AVRInstrInfo &TII = (const AVRInstrInfo &)*MI.getParent() local
[all...]
/freebsd-13-stable/contrib/llvm-project/llvm/lib/Target/SystemZ/
H A DSystemZISelLowering.cpp710 const SystemZInstrInfo *TII = local
750 if (TII->isRxSBGMask(Value, SplatBitSize, Start, End)) {
7020 const SystemZInstrInfo *TII) {
7029 BuildMI(*MBB, MI, MI.getDebugLoc(), TII->get(SystemZ::LA), Reg)
7089 const TargetInstrInfo *TII = MF->getSubtarget().getInstrInfo(); local
7123 BuildMI(*SinkMBB, SinkInsertionPoint, DL, TII->get(SystemZ::PHI), DestReg)
7139 const SystemZInstrInfo *TII = local
7202 BuildMI(MBB, MI.getDebugLoc(), TII->get(SystemZ::BRC))
7236 const SystemZInstrInfo *TII = local
7247 StoreOpcode = TII
7019 forceReg(MachineInstr &MI, MachineOperand &Base, const SystemZInstrInfo *TII) argument
7327 const SystemZInstrInfo *TII = local
7446 const SystemZInstrInfo *TII = local
7561 const SystemZInstrInfo *TII = local
7685 const SystemZInstrInfo *TII = local
7713 const SystemZInstrInfo *TII = local
7743 const SystemZInstrInfo *TII = local
7924 const SystemZInstrInfo *TII = local
7985 const SystemZInstrInfo *TII = Subtarget.getInstrInfo(); local
8032 const SystemZInstrInfo *TII = local
8056 const SystemZInstrInfo *TII = local
[all...]
/freebsd-13-stable/contrib/llvm-project/llvm/include/llvm/CodeGen/
H A DRegisterScavenging.h36 const TargetInstrInfo *TII; member in class:llvm::RegScavenger

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