Searched refs:TII (Results 26 - 50 of 403) sorted by relevance

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/freebsd-13-stable/contrib/llvm-project/llvm/lib/Target/SystemZ/
H A DSystemZCopyPhysRegs.cpp40 : MachineFunctionPass(ID), TII(nullptr), MRI(nullptr) {
53 const SystemZInstrInfo *TII; member in class:__anon4322::SystemZCopyPhysRegs
92 BuildMI(MBB, MI, DL, TII->get(SystemZ::IPM), Tmp);
94 BuildMI(MBB, MI, DL, TII->get(SystemZ::EAR), Tmp).addReg(SrcReg);
102 BuildMI(MBB, MBBI, DL, TII->get(SystemZ::SAR), DstReg).addReg(Tmp);
111 TII = static_cast<const SystemZInstrInfo *>(F.getSubtarget().getInstrInfo());
H A DSystemZLDCleanup.cpp33 : MachineFunctionPass(ID), TII(nullptr), MF(nullptr) {}
47 const SystemZInstrInfo *TII; member in class:__anon4337::SystemZLDCleanup
69 TII = static_cast<const SystemZInstrInfo *>(F.getSubtarget().getInstrInfo());
120 TII->get(TargetOpcode::COPY), SystemZ::R2D)
140 TII->get(TargetOpcode::COPY), *TLSBaseAddrReg)
/freebsd-13-stable/contrib/llvm-project/llvm/lib/Target/X86/
H A DX86LoadValueInjectionRetHardening.cpp74 const X86InstrInfo *TII = Subtarget->getInstrInfo(); local
111 BuildMI(MBB, MBB.end(), DebugLoc(), TII->get(X86::POP64r))
114 BuildMI(MBB, MBB.end(), DebugLoc(), TII->get(X86::LFENCE));
115 BuildMI(MBB, MBB.end(), DebugLoc(), TII->get(X86::JMP64r))
122 MachineInstr *Fence = BuildMI(MBB, MI, DebugLoc(), TII->get(X86::LFENCE));
123 addRegOffset(BuildMI(MBB, Fence, DebugLoc(), TII->get(X86::SHL64mi)),
H A DX86FixupSetCC.cpp49 const X86InstrInfo *TII = nullptr; member in class:__anon4430::X86FixupSetCCPass
64 TII = MF.getSubtarget<X86Subtarget>().getInstrInfo();
111 BuildMI(MBB, FlagsDefMI, MI.getDebugLoc(), TII->get(X86::MOV32r0),
117 TII->get(X86::INSERT_SUBREG), InsertReg)
/freebsd-13-stable/contrib/llvm-project/llvm/lib/Target/XCore/
H A DXCoreRegisterInfo.cpp62 const XCoreInstrInfo &TII,
70 BuildMI(MBB, II, dl, TII.get(XCore::LDW_2rus), Reg)
76 BuildMI(MBB, II, dl, TII.get(XCore::STW_2rus))
83 BuildMI(MBB, II, dl, TII.get(XCore::LDAWF_l2rus), Reg)
93 const XCoreInstrInfo &TII,
102 TII.loadImmediate(MBB, II, ScratchOffset, Offset);
106 BuildMI(MBB, II, dl, TII.get(XCore::LDW_3r), Reg)
112 BuildMI(MBB, II, dl, TII.get(XCore::STW_l3r))
119 BuildMI(MBB, II, dl, TII.get(XCore::LDAWF_l3r), Reg)
129 const XCoreInstrInfo &TII,
61 InsertFPImmInst(MachineBasicBlock::iterator II, const XCoreInstrInfo &TII, unsigned Reg, unsigned FrameReg, int Offset ) argument
92 InsertFPConstInst(MachineBasicBlock::iterator II, const XCoreInstrInfo &TII, unsigned Reg, unsigned FrameReg, int Offset, RegScavenger *RS ) argument
128 InsertSPImmInst(MachineBasicBlock::iterator II, const XCoreInstrInfo &TII, unsigned Reg, int Offset) argument
161 InsertSPConstInst(MachineBasicBlock::iterator II, const XCoreInstrInfo &TII, unsigned Reg, int Offset, RegScavenger *RS ) argument
263 const XCoreInstrInfo &TII = local
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/freebsd-13-stable/contrib/llvm-project/llvm/lib/Target/AMDGPU/
H A DGCNDPPCombine.cpp68 const SIInstrInfo *TII; member in class:__anon3942::GCNDPPCombine
135 return (DPP32 == -1 || TII->pseudoToMCOpcode(DPP32) == -1) ? -1 : DPP32;
176 OrigMI.getDebugLoc(), TII->get(DPPOp))
181 auto *Dst = TII->getNamedOperand(OrigMI, AMDGPU::OpName::vdst);
202 if (auto *Mod0 = TII->getNamedOperand(OrigMI,
214 auto *Src0 = TII->getNamedOperand(MovMI, AMDGPU::OpName::src0);
216 if (!TII->isOperandLegal(*DPPInst.getInstr(), NumOperands, Src0)) {
225 if (auto *Mod1 = TII->getNamedOperand(OrigMI,
237 if (auto *Src1 = TII->getNamedOperand(OrigMI, AMDGPU::OpName::src1)) {
238 if (!TII
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H A DAMDGPUExportClustering.cpp35 static bool isPositionExport(const SIInstrInfo *TII, SUnit *SU) { argument
37 int Imm = TII->getNamedOperand(*MI, AMDGPU::OpName::tgt)->getImm();
41 static void sortChain(const SIInstrInfo *TII, SmallVector<SUnit *, 8> &Chain, argument
54 if (isPositionExport(TII, SU))
111 const SIInstrInfo *TII = static_cast<const SIInstrInfo *>(DAG->TII); local
125 if (isPositionExport(TII, &SU))
137 sortChain(TII, Chain, PosCount);
H A DAMDGPUMacroFusion.cpp32 const SIInstrInfo &TII = static_cast<const SIInstrInfo&>(TII_); local
48 const MachineOperand *Src2 = TII.getNamedOperand(SecondMI,
H A DSIFixVGPRCopies.cpp51 const SIInstrInfo *TII = ST.getInstrInfo(); local
58 if (TII->isVGPRCopy(MI) && !MI.readsRegister(AMDGPU::EXEC, TRI)) {
H A DSIFixupVectorISel.cpp159 const SIInstrInfo *TII,
177 MachineOperand *Op = TII->getNamedOperand(MI, AMDGPU::OpName::vaddr);
183 bool HasVdst = TII->getNamedOperand(MI, AMDGPU::OpName::vdst) != nullptr;
184 MachineOperand *VData = TII->getNamedOperand(MI, AMDGPU::OpName::vdata);
186 NewGlob = BuildMI(MBB, I, MI.getDebugLoc(), TII->get(NewOpcd));
193 NewGlob->addOperand(*TII->getNamedOperand(MI, AMDGPU::OpName::offset));
195 MachineOperand *Glc = TII->getNamedOperand(MI, AMDGPU::OpName::glc);
200 MachineOperand *DLC = TII->getNamedOperand(MI, AMDGPU::OpName::dlc);
204 NewGlob->addOperand(*TII->getNamedOperand(MI, AMDGPU::OpName::slc));
206 MachineOperand *VDstInOp = TII
155 fixupGlobalSaddr(MachineBasicBlock &MBB, MachineFunction &MF, MachineRegisterInfo &MRI, const GCNSubtarget &ST, const SIInstrInfo *TII, const SIRegisterInfo *TRI) argument
230 const SIInstrInfo *TII = ST.getInstrInfo(); local
[all...]
H A DSILoadStoreOptimizer.cpp185 void setMI(MachineBasicBlock::iterator MI, const SIInstrInfo &TII,
206 const SIInstrInfo *TII = nullptr; member in class:__anon3979::SILoadStoreOptimizer
213 const SIInstrInfo &TII,
306 static unsigned getOpcodeWidth(const MachineInstr &MI, const SIInstrInfo &TII) { argument
309 if (TII.isMUBUF(Opc)) {
313 if (TII.isMIMG(MI)) {
315 TII.getNamedOperand(MI, AMDGPU::OpName::dmask)->getImm();
318 if (TII.isMTBUF(Opc)) {
335 static InstClassEnum getInstClass(unsigned Opc, const SIInstrInfo &TII) { argument
338 if (TII
401 getInstSubclass(unsigned Opc, const SIInstrInfo &TII) argument
430 getRegs(unsigned Opc, const SIInstrInfo &TII) argument
491 setMI(MachineBasicBlock::iterator MI, const SIInstrInfo &TII, const GCNSubtarget &STM) argument
679 dmasksCanBeCombined(const CombineInfo &CI, const SIInstrInfo &TII, const CombineInfo &Paired) argument
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/freebsd-13-stable/contrib/llvm-project/llvm/include/llvm/CodeGen/
H A DPseudoSourceValue.h62 explicit PseudoSourceValue(unsigned Kind, const TargetInstrInfo &TII);
98 explicit FixedStackPseudoSourceValue(int FI, const TargetInstrInfo &TII) argument
99 : PseudoSourceValue(FixedStack, TII), FI(FI) {}
118 CallEntryPseudoSourceValue(unsigned Kind, const TargetInstrInfo &TII);
132 const TargetInstrInfo &TII);
146 ExternalSymbolPseudoSourceValue(const char *ES, const TargetInstrInfo &TII);
157 const TargetInstrInfo &TII; member in class:llvm::PseudoSourceValueManager
167 PseudoSourceValueManager(const TargetInstrInfo &TII);
H A DMacroFusion.h30 using ShouldSchedulePredTy = std::function<bool(const TargetInstrInfo &TII,
/freebsd-13-stable/contrib/llvm-project/llvm/lib/Target/Hexagon/
H A DHexagonHazardRecognizer.h24 const HexagonInstrInfo *TII; member in class:llvm::HexagonHazardRecognizer
47 : Resources(ST.createDFAPacketizer(II)), TII(HII) { }
/freebsd-13-stable/contrib/llvm-project/llvm/lib/Target/ARM/
H A DARMInstructionSelector.cpp73 const ARMBaseInstrInfo &TII; member in class:__anon4027::ARMInstructionSelector
176 : InstructionSelector(), TII(*STI.getInstrInfo()),
213 static bool selectCopy(MachineInstr &I, const TargetInstrInfo &TII, argument
226 LLVM_DEBUG(dbgs() << "Failed to constrain " << TII.getName(I.getOpcode())
234 const ARMBaseInstrInfo &TII,
238 assert(TII.getSubtarget().hasVFP2Base() && "Can't select merge without VFP");
258 MIB->setDesc(TII.get(ARM::VMOVDRR));
265 const ARMBaseInstrInfo &TII,
269 assert(TII.getSubtarget().hasVFP2Base() &&
290 MIB->setDesc(TII
233 selectMergeValues(MachineInstrBuilder &MIB, const ARMBaseInstrInfo &TII, MachineRegisterInfo &MRI, const TargetRegisterInfo &TRI, const RegisterBankInfo &RBI) argument
264 selectUnmergeValues(MachineInstrBuilder &MIB, const ARMBaseInstrInfo &TII, MachineRegisterInfo &MRI, const TargetRegisterInfo &TRI, const RegisterBankInfo &RBI) argument
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H A DARMFrameLowering.cpp147 const DebugLoc &dl, const ARMBaseInstrInfo &TII, unsigned DestReg,
152 Pred, PredReg, TII, MIFlags);
155 Pred, PredReg, TII, MIFlags);
160 const ARMBaseInstrInfo &TII, int NumBytes,
164 emitRegPlusImmediate(isARM, MBB, MBBI, dl, TII, ARM::SP, ARM::SP, NumBytes,
231 const ARMBaseInstrInfo &TII, bool HasFP) {
242 TII.get(TargetOpcode::CFI_INSTRUCTION))
259 const TargetInstrInfo &TII,
282 BuildMI(MBB, MBBI, DL, TII.get(ARM::BFC), Reg)
287 BuildMI(MBB, MBBI, DL, TII
145 emitRegPlusImmediate( bool isARM, MachineBasicBlock &MBB, MachineBasicBlock::iterator &MBBI, const DebugLoc &dl, const ARMBaseInstrInfo &TII, unsigned DestReg, unsigned SrcReg, int NumBytes, unsigned MIFlags = MachineInstr::NoFlags, ARMCC::CondCodes Pred = ARMCC::AL, unsigned PredReg = 0) argument
158 emitSPUpdate(bool isARM, MachineBasicBlock &MBB, MachineBasicBlock::iterator &MBBI, const DebugLoc &dl, const ARMBaseInstrInfo &TII, int NumBytes, unsigned MIFlags = MachineInstr::NoFlags, ARMCC::CondCodes Pred = ARMCC::AL, unsigned PredReg = 0) argument
230 emitDefCFAOffsets(MachineBasicBlock &MBB, const DebugLoc &dl, const ARMBaseInstrInfo &TII, bool HasFP) argument
258 emitAligningInstructions(MachineFunction &MF, ARMFunctionInfo *AFI, const TargetInstrInfo &TII, MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI, const DebugLoc &DL, const unsigned Reg, const Align Alignment, const bool MustBeSingleInstruction) argument
346 const ARMBaseInstrInfo &TII = *STI.getInstrInfo(); local
770 const ARMBaseInstrInfo &TII = local
981 const TargetInstrInfo &TII = *MF.getSubtarget().getInstrInfo(); local
1058 const TargetInstrInfo &TII = *MF.getSubtarget().getInstrInfo(); local
1176 const TargetInstrInfo &TII = *MF.getSubtarget().getInstrInfo(); local
1349 const TargetInstrInfo &TII = *MF.getSubtarget().getInstrInfo(); local
1501 EstimateFunctionSizeInBytes(const MachineFunction &MF, const ARMBaseInstrInfo &TII) argument
1523 const ARMBaseInstrInfo &TII = local
1674 const ARMBaseInstrInfo &TII = local
2195 const ARMBaseInstrInfo &TII = local
2310 const ARMBaseInstrInfo &TII = local
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/freebsd-13-stable/contrib/llvm-project/llvm/lib/CodeGen/
H A DPatchableFunction.cpp60 const TargetInstrInfo *TII = MF.getSubtarget().getInstrInfo(); local
63 TII->get(TargetOpcode::PATCHABLE_FUNCTION_ENTER));
81 auto *TII = MF.getSubtarget().getInstrInfo(); local
83 TII->get(TargetOpcode::PATCHABLE_OP))
/freebsd-13-stable/contrib/llvm-project/llvm/lib/Target/ARC/
H A DARCExpandPseudos.cpp39 const ARCInstrInfo *TII; member in class:__anon4001::ARCExpandPseudos
65 BuildMI(*SI.getParent(), SI, SI.getDebugLoc(), TII->get(AddOpc), AddrReg)
69 TII->get(getMappedOp(SI.getOpcode())))
78 TII = STI->getInstrInfo();
/freebsd-13-stable/contrib/llvm-project/llvm/lib/Target/RISCV/
H A DRISCVExpandAtomicPseudoInsts.cpp33 const RISCVInstrInfo *TII; member in class:__anon4294::RISCVExpandAtomicPseudo
66 TII = static_cast<const RISCVInstrInfo *>(MF.getSubtarget().getInstrInfo());
216 static void doAtomicBinOpExpansion(const RISCVInstrInfo *TII, MachineInstr &MI, argument
233 BuildMI(LoopMBB, DL, TII->get(getLRForRMW(Ordering, Width)), DestReg)
239 BuildMI(LoopMBB, DL, TII->get(RISCV::AND), ScratchReg)
242 BuildMI(LoopMBB, DL, TII->get(RISCV::XORI), ScratchReg)
247 BuildMI(LoopMBB, DL, TII->get(getSCForRMW(Ordering, Width)), ScratchReg)
250 BuildMI(LoopMBB, DL, TII->get(RISCV::BNE))
256 static void insertMaskedMerge(const RISCVInstrInfo *TII, DebugLoc DL, argument
267 BuildMI(MBB, DL, TII
278 doMaskedAtomicBinOpExpansion( const RISCVInstrInfo *TII, MachineInstr &MI, DebugLoc DL, MachineBasicBlock *ThisMBB, MachineBasicBlock *LoopMBB, MachineBasicBlock *DoneMBB, AtomicRMWInst::BinOp BinOp, int Width) argument
379 insertSext(const RISCVInstrInfo *TII, DebugLoc DL, MachineBasicBlock *MBB, Register ValReg, Register ShamtReg) argument
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/freebsd-13-stable/contrib/llvm-project/llvm/lib/Target/Sparc/
H A DSparcRegisterInfo.cpp123 const TargetInstrInfo &TII = *MF.getSubtarget().getInstrInfo(); local
132 BuildMI(*MI.getParent(), II, dl, TII.get(SP::SETHIi), SP::G1)
137 BuildMI(*MI.getParent(), II, dl, TII.get(SP::ADDrr), SP::G1).addReg(SP::G1)
150 BuildMI(*MI.getParent(), II, dl, TII.get(SP::SETHIi), SP::G1)
152 BuildMI(*MI.getParent(), II, dl, TII.get(SP::XORri), SP::G1)
155 BuildMI(*MI.getParent(), II, dl, TII.get(SP::ADDrr), SP::G1).addReg(SP::G1)
184 const TargetInstrInfo &TII = *Subtarget.getInstrInfo(); local
189 BuildMI(*MI.getParent(), II, dl, TII.get(SP::STDFri))
192 MI.setDesc(TII.get(SP::STDFri));
196 const TargetInstrInfo &TII local
[all...]
H A DLeonPasses.cpp42 const TargetInstrInfo &TII = *Subtarget->getInstrInfo(); local
53 BuildMI(MBB, NMBBI, DL, TII.get(SP::NOP));
129 const TargetInstrInfo &TII = *Subtarget->getInstrInfo(); local
145 BuildMI(MBB, MBBI, DL, TII.get(SP::NOP));
149 BuildMI(MBB, NMBBI, DL, TII.get(SP::NOP));
/freebsd-13-stable/contrib/llvm-project/llvm/lib/Target/Mips/
H A DMipsBranchExpansion.cpp167 const MipsInstrInfo *TII; member in class:__anon4214::MipsBranchExpansion
299 MBBInfos[I].Size += TII->getInstSizeInBytes(*MI);
337 unsigned NewOpc = TII->getOppositeBranchOpc(Br->getOpcode());
338 const MCInstrDesc &NewDesc = TII->get(NewOpc);
352 if (!TII->isBranchWithImm(Br->getOpcode()))
396 BuildMI(*MBB, Pos, DL, TII->get(JumpOp)).addReg(ATReg);
465 BuildMI(*LongBrMBB, Pos, DL, TII->get(Mips::ADDiu), Mips::SP)
468 BuildMI(*LongBrMBB, Pos, DL, TII->get(Mips::SW))
489 BuildMI(*LongBrMBB, Pos, DL, TII->get(Mips::LONG_BRANCH_LUi), Mips::AT)
494 BuildMI(*MFp, DL, TII
729 emitGPDisp(MachineFunction &F, const MipsInstrInfo *TII) argument
[all...]
H A DMips16RegisterInfo.cpp61 const TargetInstrInfo &TII = *MBB.getParent()->getSubtarget().getInstrInfo(); local
62 TII.copyPhysReg(MBB, I, DL, Mips::T0, Reg, true);
63 TII.copyPhysReg(MBB, UseMI, DL, Reg, Mips::T0, true);
135 const Mips16InstrInfo &TII = local
137 FrameReg = TII.loadImmediate(FrameReg, Offset, MBB, II, DL, NewImm);
/freebsd-13-stable/contrib/llvm-project/llvm/lib/Target/WebAssembly/
H A DWebAssemblyFrameLowering.cpp180 const auto *TII = MF.getSubtarget<WebAssemblySubtarget>().getInstrInfo(); local
185 BuildMI(MBB, InsertStore, DL, TII->get(getOpcGlobSet(MF)))
197 const auto *TII = ST.getInstrInfo(); local
198 if (I->getOpcode() == TII->getCallFrameDestroyOpcode() &&
218 const auto *TII = ST.getInstrInfo(); local
235 BuildMI(MBB, InsertPt, DL, TII->get(getOpcGlobGet(MF)), SPReg)
243 BuildMI(MBB, InsertPt, DL, TII->get(WebAssembly::COPY), BasePtr)
249 BuildMI(MBB, InsertPt, DL, TII->get(getOpcConst(MF)), OffsetReg)
251 BuildMI(MBB, InsertPt, DL, TII->get(getOpcSub(MF)), getSPReg(MF))
258 BuildMI(MBB, InsertPt, DL, TII
282 const auto *TII = ST.getInstrInfo(); local
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/freebsd-13-stable/contrib/llvm-project/llvm/lib/Target/AArch64/
H A DAArch64StorePairSuppress.cpp31 const AArch64InstrInfo *TII; member in class:__anon3877::AArch64StorePairSuppress
85 unsigned SCIdx = TII->get(AArch64::STPDi).getSchedClass();
126 TII = static_cast<const AArch64InstrInfo *>(ST.getInstrInfo());
153 if (TII->getMemOperandWithOffset(MI, BaseOp, Offset, OffsetIsScalable,
164 TII->suppressLdStPair(MI);

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