Searched refs:TII (Results 101 - 125 of 403) sorted by relevance

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/freebsd-13-stable/contrib/llvm-project/llvm/lib/Target/ARM/
H A DARMExpandPseudoInsts.cpp44 const ARMBaseInstrInfo *TII; member in class:__anon4013::ARMExpandPseudo
511 TII->get(TableEntry->RealOpc));
622 TII->get(TableEntry->RealOpc));
699 TII->get(TableEntry->RealOpc));
783 MachineInstrBuilder MIB = BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(Opc));
877 LO16 = BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(ARM::MOVi), DstReg);
878 HI16 = BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(ARM::ORRri))
913 LO16 = BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(LO16Opc), DstReg);
914 HI16 = BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(HI16Opc))
989 BuildMI(MBB, MBBI, DL, TII
1766 CMSEPushCalleeSaves(const TargetInstrInfo &TII, MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI, int JumpReg, const LivePhysRegs &LiveRegs, bool Thumb1Only) argument
1826 CMSEPopCalleeSaves(const TargetInstrInfo &TII, MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI, int JumpReg, bool Thumb1Only) argument
1870 const ARMBaseInstrInfo &TII = *static_cast<const ARMBaseInstrInfo *>( local
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H A DARMMacroFusion.cpp51 static bool shouldScheduleAdjacent(const TargetInstrInfo &TII, argument
/freebsd-13-stable/contrib/llvm-project/llvm/lib/Target/PowerPC/
H A DPPCEarlyReturn.cpp49 const TargetInstrInfo *TII; member in struct:__anon4262::PPCEarlyReturn
80 BuildMI(**PI, J, J->getDebugLoc(), TII->get(I->getOpcode()))
92 BuildMI(**PI, J, J->getDebugLoc(), TII->get(PPC::BCCLR))
108 TII->get(J->getOpcode() == PPC::BC ? PPC::BCLR : PPC::BCLRn))
174 TII = MF.getSubtarget().getInstrInfo();
H A DPPCVSXCopy.cpp49 const TargetInstrInfo *TII; member in struct:__anon4284::PPCVSXCopy
107 TII->get(TargetOpcode::SUBREG_TO_REG), NewVReg)
128 BuildMI(MBB, MI, MI.getDebugLoc(), TII->get(TargetOpcode::COPY),
147 TII = STI.getInstrInfo();
/freebsd-13-stable/contrib/llvm-project/llvm/lib/Target/WebAssembly/
H A DWebAssemblyPeephole.cpp78 const WebAssemblyInstrInfo &TII) {
121 BuildMI(MBB, MI, MI.getDebugLoc(), TII.get(CopyLocalOpc), NewReg)
128 MI.setDesc(TII.get(WebAssembly::FALLTHROUGH_RETURN));
140 const auto &TII = *MF.getSubtarget<WebAssemblySubtarget>().getInstrInfo(); local
180 Changed |= maybeRewriteToFallthrough(MI, MBB, MF, MFI, MRI, TII);
74 maybeRewriteToFallthrough(MachineInstr &MI, MachineBasicBlock &MBB, const MachineFunction &MF, WebAssemblyFunctionInfo &MFI, MachineRegisterInfo &MRI, const WebAssemblyInstrInfo &TII) argument
H A DWebAssemblyFixBrTableDefaults.cpp60 const auto &TII = *MF.getSubtarget<WebAssemblySubtarget>().getInstrInfo(); local
61 bool Analyzed = !TII.analyzeBranch(*HeaderMBB, TBB, FBB, Cond);
96 TII.removeBranch(*HeaderMBB, nullptr);
/freebsd-13-stable/contrib/llvm-project/llvm/lib/CodeGen/
H A DPeepholeOptimizer.cpp155 const TargetInstrInfo *TII; member in class:__anon3540::PeepholeOptimizer
382 const TargetInstrInfo *TII;
420 const TargetInstrInfo *TII = nullptr)
421 : DefSubReg(DefSubReg), Reg(Reg), MRI(MRI), TII(TII) {
462 if (!TII->isCoalescableExtInstr(MI, SrcReg, DstReg, SubIdx))
587 TII->get(TargetOpcode::COPY), NewVR)
612 if (!TII->analyzeCompare(MI, SrcReg, SrcReg2, CmpMask, CmpValue) ||
618 if (TII->optimizeCompareInstr(MI, SrcReg, SrcReg2, CmpMask, CmpValue, MRI)) {
634 if (TII
758 insertPHI(MachineRegisterInfo &MRI, const TargetInstrInfo &TII, const SmallVectorImpl<RegSubRegPair> &SrcRegs, MachineInstr &OrigPHI) argument
957 const TargetInstrInfo &TII; member in class:__anon3540::ValueTrackerResult::__anon3541::ExtractSubregRewriter
960 ExtractSubregRewriter(MachineInstr &MI, const TargetInstrInfo &TII) argument
1087 getCopyRewriter(MachineInstr &MI, const TargetInstrInfo &TII) argument
1114 getNewSource(MachineRegisterInfo *MRI, const TargetInstrInfo *TII, RegSubRegPair Def, const PeepholeOptimizer::RewriteMapTy &RewriteMap, bool HandleMultipleSources = true) argument
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H A DBreakFalseDeps.cpp36 const TargetInstrInfo *TII; member in class:llvm::BreakFalseDeps
135 TII->getRegClass(MI->getDesc(), OpIdx, TRI, *MF);
192 unsigned Pref = TII->getUndefRegClearance(*MI, OpNum, TRI);
217 unsigned Pref = TII->getPartialRegUpdateClearance(*MI, i, TRI);
219 TII->breakPartialRegDependency(*MI, i, TRI);
247 TII->breakPartialRegDependency(*UndefMI, OpIdx, TRI);
276 TII = MF->getSubtarget().getInstrInfo();
/freebsd-13-stable/contrib/llvm-project/llvm/lib/Target/AMDGPU/
H A DAMDGPUInstructionSelector.cpp57 : InstructionSelector(), TII(*STI.getInstrInfo()),
98 MI.setDesc(TII.get(NewOpc));
123 I.setDesc(TII.get(TargetOpcode::COPY));
155 BuildMI(*BB, &I, DL, TII.get(AndOpc), MaskedReg)
158 BuildMI(*BB, &I, DL, TII.get(AMDGPU::V_CMP_NE_U32_e64), DstReg)
236 I.setDesc(TII.get(TargetOpcode::PHI));
252 BuildMI(*BB, MI, MI->getDebugLoc(), TII.get(AMDGPU::COPY), DstReg)
300 I.setDesc(TII.get(InstOpc));
323 I.setDesc(TII.get(InstOpc));
329 return constrainSelectedInstRegOperands(I, TII, TR
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H A DSIPreEmitPeephole.cpp30 const SIInstrInfo *TII = nullptr; member in class:__anon3992::SIPreEmitPeephole
97 TII->commuteInstruction(*A);
150 MI.setDesc(TII->get(AMDGPU::S_BRANCH));
178 MI.setDesc(TII->get(AMDGPU::S_BRANCH));
189 TII->get(IsVCCZ ? AMDGPU::S_CBRANCH_EXECZ : AMDGPU::S_CBRANCH_EXECNZ));
203 MachineOperand *Idx = TII->getNamedOperand(MI, AMDGPU::OpName::src0);
250 TII = ST.getInstrInfo();
251 TRI = &TII->getRegisterInfo();
288 BuildMI(MBB, &MI, MI.getDebugLoc(), TII->get(AMDGPU::S_BRANCH))
H A DSILowerControlFlow.cpp87 const SIInstrInfo *TII = nullptr; member in class:__anon3980::SILowerControlFlow
168 const MachineBasicBlock *End, const SIInstrInfo *TII) {
179 if (TII->isKillTerminator(Term.getOpcode()))
232 if (hasKill(MI.getParent(), UseMI->getParent(), TII)) {
241 SimpleIf = !hasKill(MI.getParent(), UseMI->getParent(), TII);
249 BuildMI(MBB, I, DL, TII->get(AMDGPU::COPY), CopyReg)
257 BuildMI(MBB, I, DL, TII->get(AndOpc), Tmp)
266 BuildMI(MBB, I, DL, TII->get(XorOpc), SaveExecReg)
275 BuildMI(MBB, I, DL, TII->get(MovTermOpc), Exec)
280 MachineInstr *NewBr = BuildMI(MBB, I, DL, TII
167 hasKill(const MachineBasicBlock *Begin, const MachineBasicBlock *End, const SIInstrInfo *TII) argument
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/freebsd-13-stable/contrib/llvm-project/llvm/lib/Target/Hexagon/
H A DHexagonCopyToCombine.cpp60 const HexagonInstrInfo *TII; member in class:__anon4116::HexagonCopyToCombine
127 static bool isCombinableInstType(MachineInstr &MI, const HexagonInstrInfo *TII, argument
402 if (TII->mayBeNewStore(MI)) {
417 if (!isCombinableInstType(*DefInst, TII, ShouldCombineAggressively))
471 TII = ST->getInstrInfo();
505 if (!isCombinableInstType(I1, TII, ShouldCombineAggressively))
544 if (!isCombinableInstType(*I2, TII, ShouldCombineAggressively))
663 BuildMI(*BB, InsertPt, DL, TII->get(Hexagon::CONST64), DoubleDestReg)
676 BuildMI(*BB, InsertPt, DL, TII->get(Hexagon::A2_combineii), DoubleDestReg)
683 BuildMI(*BB, InsertPt, DL, TII
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H A DHexagonSplitDouble.cpp85 const HexagonInstrInfo *TII = nullptr; member in class:__anon4148::HexagonSplitDoubleRegs
488 bool BadLB = TII->analyzeBranch(*TmpLB, TB, FB, Cond, false);
495 if (!TII->PredOpcodeHasJMP_c(Cond[0].getImm()))
513 bool OkCI = TII->analyzeCompare(*CmpI, CmpR1, CmpR2, Mask, Val);
598 MachineInstr *NewI = BuildMI(B, MI, DL, TII->get(Opc));
652 LowI = BuildMI(B, MI, DL, TII->get(Hexagon::L2_loadri_io), P.first)
655 HighI = BuildMI(B, MI, DL, TII->get(Hexagon::L2_loadri_io), P.second)
661 LowI = BuildMI(B, MI, DL, TII->get(Hexagon::S2_storeri_io))
665 HighI = BuildMI(B, MI, DL, TII->get(Hexagon::S2_storeri_io))
679 BuildMI(B, MI, DL, TII
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/freebsd-13-stable/contrib/llvm-project/llvm/lib/Target/AArch64/
H A DAArch64LoadStoreOptimizer.cpp116 const AArch64InstrInfo *TII; member in struct:AArch64LoadStoreOpt
579 const AArch64InstrInfo *TII) {
581 int LoadSize = TII->getMemScale(LoadInst);
582 int StoreSize = TII->getMemScale(StoreInst);
583 int UnscaledStOffset = TII->isUnscaledLdSt(StoreInst)
586 int UnscaledLdOffset = TII->isUnscaledLdSt(LoadInst)
691 bool IsScaled = !TII->isUnscaledLdSt(Opc);
692 int OffsetStride = IsScaled ? 1 : TII->getMemScale(*I);
722 MIB = BuildMI(*MBB, InsertionPoint, DL, TII->get(getMatchingWideOpcode(Opc)))
797 bool IsUnscaled = TII
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/freebsd-13-stable/contrib/llvm-project/llvm/lib/Target/AVR/
H A DAVRRegisterInfo.cpp142 const TargetInstrInfo &TII = *TM.getSubtargetImpl()->getInstrInfo(); local
157 MI.setDesc(TII.get(AVR::MOVWRdRr));
200 MachineInstr *New = BuildMI(MBB, II, dl, TII.get(Opcode), DstReg)
226 BuildMI(MBB, II, dl, TII.get(AVR::INRdA), AVR::R0).addImm(0x3f);
228 MachineInstr *New = BuildMI(MBB, II, dl, TII.get(AddOpc), AVR::R29R28)
234 BuildMI(MBB, std::next(II), dl, TII.get(AVR::OUTARr))
240 BuildMI(MBB, std::next(II), dl, TII.get(SubOpc), AVR::R29R28)
H A DAVRRelaxMemOperations.cpp46 const TargetInstrInfo *TII; member in class:__anon4065::AVRRelaxMem
54 return BuildMI(MBB, MBBI, MBBI->getDebugLoc(), TII->get(Opcode));
64 TII = STI.getInstrInfo();
/freebsd-13-stable/contrib/llvm-project/llvm/lib/Target/X86/
H A DX86DomainReassignment.cpp93 const TargetInstrInfo *TII) const {
102 virtual bool convertInstr(MachineInstr *MI, const TargetInstrInfo *TII,
117 bool convertInstr(MachineInstr *MI, const TargetInstrInfo *TII,
119 assert(isLegal(MI, TII) && "Cannot convert instruction");
139 const TargetInstrInfo *TII) const override {
140 if (!InstrConverterBase::isLegal(MI, TII))
146 !TII->get(DstOpcode).hasImplicitDefOfPhysReg(MO.getReg()))
151 bool convertInstr(MachineInstr *MI, const TargetInstrInfo *TII,
153 assert(isLegal(MI, TII) && "Cannot convert instruction");
155 BuildMI(*MI->getParent(), MI, MI->getDebugLoc(), TII
378 const X86InstrInfo *TII = nullptr; member in class:__anon4424::X86DomainReassignment
526 usedAsAddr(const MachineInstr &MI, unsigned Reg, const TargetInstrInfo *TII) argument
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H A DX86WinAllocaExpander.cpp60 const TargetInstrInfo *TII = nullptr; member in class:__anon4466::X86WinAllocaExpander
221 BuildMI(*MBB, I, DL, TII->get(Is64Bit ? X86::PUSH64r : X86::PUSH32r))
235 BuildMI(*MBB, I, DL, TII->get(Is64Bit ? X86::PUSH64r : X86::PUSH32r))
240 TII->get(getSubOpcode(Is64BitAlloca, Amount)), StackPtr)
249 BuildMI(*MBB, MI, DL, TII->get(TargetOpcode::COPY), RegA)
258 TII->get(Is64BitAlloca ? X86::SUB64rr : X86::SUB32rr), StackPtr)
280 TII = STI->getInstrInfo();
H A DX86SpeculativeLoadHardening.cpp164 const X86InstrInfo *TII = nullptr; member in class:__anon4463::X86SpeculativeLoadHardeningPass
227 const X86InstrInfo &TII) {
255 BuildMI(&MBB, DebugLoc(), TII.get(X86::JMP_1)).addMBB(&OldLayoutSucc);
264 TII.insertBranch(NewMBB, &Succ, nullptr, Cond, Br->getDebugLoc());
411 TII = Subtarget->getInstrInfo();
448 BuildMI(Entry, EntryInsertPt, Loc, TII->get(X86::MOV64ri32), PS->PoisonReg)
461 BuildMI(Entry, EntryInsertPt, Loc, TII->get(X86::LFENCE));
482 auto ZeroI = BuildMI(Entry, EntryInsertPt, Loc, TII->get(X86::MOV32r0),
490 BuildMI(Entry, EntryInsertPt, Loc, TII->get(X86::SUBREG_TO_REG),
592 BuildMI(*MBB, InsertPt, DebugLoc(), TII
224 splitEdge(MachineBasicBlock &MBB, MachineBasicBlock &Succ, int SuccCount, MachineInstr *Br, MachineInstr *&UncondBr, const X86InstrInfo &TII) argument
841 getRegClassForUnfoldedLoad(MachineFunction &MF, const X86InstrInfo &TII, unsigned Opcode) argument
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H A DX86FixupLEAs.cpp125 const X86InstrInfo *TII = nullptr; member in class:__anon4429::FixupLEAPass
145 TII->get(MI.getOpcode() == X86::MOV32rr ? X86::LEA32r
192 return TII->convertToThreeAddress(MFI, MI, nullptr);
215 TII = ST.getInstrInfo();
379 !TII->isSafeToClobberEFLAGS(MBB, I))
410 NewMI = BuildMI(MBB, I, MI.getDebugLoc(), TII->get(NewOpcode), DestReg)
415 NewMI = BuildMI(MBB, I, MI.getDebugLoc(), TII->get(NewOpcode), DestReg)
431 NewMI = BuildMI(MBB, I, MI.getDebugLoc(), TII->get(NewOpcode), DestReg)
434 NewMI = BuildMI(MBB, I, MI.getDebugLoc(), TII->get(NewOpcode), DestReg)
441 NewMI = BuildMI(MBB, I, MI.getDebugLoc(), TII
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H A DX86IndirectBranchTracking.cpp52 const X86InstrInfo *TII = nullptr; member in class:__anon4440::X86IndirectBranchTrackingPass
74 assert(TII && "Target instruction info was not initialized");
81 BuildMI(MBB, I, MBB.findDebugLoc(I), TII->get(EndbrOpcode));
119 TII = SubTarget.getInstrInfo();
/freebsd-13-stable/contrib/llvm-project/llvm/lib/Target/SystemZ/
H A DSystemZShortenInst.cpp51 const SystemZInstrInfo *TII; member in class:__anon4340::SystemZShortenInst
64 : MachineFunctionPass(ID), TII(nullptr) {}
95 MI.setDesc(TII->get(LLIxL));
100 MI.setDesc(TII->get(LLIxH));
111 MI.setDesc(TII->get(Opcode));
122 MI.setDesc(TII->get(Opcode));
135 MI.setDesc(TII->get(Opcode));
168 MI.setDesc(TII->get(Opcode));
195 MI.setDesc(TII->get(Opcode));
362 !TII
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/freebsd-13-stable/contrib/llvm-project/llvm/include/llvm/CodeGen/GlobalISel/
H A DLegalizer.h68 const TargetInstrInfo &TII);
H A DUtils.h48 const TargetInstrInfo &TII,
62 const TargetInstrInfo &TII,
80 const TargetInstrInfo &TII,
95 const TargetInstrInfo &TII,
/freebsd-13-stable/contrib/llvm-project/llvm/lib/Target/MSP430/
H A DMSP430RegisterInfo.cpp133 const TargetInstrInfo &TII = *MF.getSubtarget().getInstrInfo(); local
135 MI.setDesc(TII.get(MSP430::MOV16rr));
144 BuildMI(MBB, std::next(II), dl, TII.get(MSP430::SUB16ri), DstReg)
147 BuildMI(MBB, std::next(II), dl, TII.get(MSP430::ADD16ri), DstReg)

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