| /freebsd-13-stable/contrib/llvm-project/llvm/lib/Target/AMDGPU/ |
| H A D | AMDGPULegalizerInfo.cpp | 1969 Register Src0 = MI.getOperand(1).getReg();
1971 LLT SrcTy = MRI.getType(Src0);
2248 Register Src0 = MI.getOperand(1).getReg();
2256 auto Log = B.buildFLog2(S32, Src0, Flags);
2264 auto Log = B.buildFLog2(S16, Src0, Flags);
2356 Register Src0 = MI.getOperand(1).getReg();
2358 assert(MRI.getType(Src0) == LLT::scalar(16));
2360 auto Merge = B.buildMerge(S32, {Src0, Src1});
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| H A D | R600InstrInfo.cpp | 1326 MachineOperand &Src0 = MI->getOperand(
1331 MBB, I, Opcode, DstReg, Src0.getReg(), Src1.getReg());
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| H A D | AMDGPUISelDAGToDAG.cpp | 2169 SDValue Src0 = N->getOperand(0); local
2176 bool Sel0 = SelectVOP3PMadMixModsImpl(Src0, Src0, Src0Mods);
2189 CurDAG->getTargetConstant(Src0Mods, SDLoc(), MVT::i32), Src0,
2441 N->getOperand(1), // Src0
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| H A D | SIInstrInfo.h | 142 MachineOperand &Src0, unsigned Src0OpName,
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| H A D | AMDGPUISelLowering.cpp | 2816 static SDValue constantFoldBFE(SelectionDAG &DAG, IntTy Src0, uint32_t Offset, argument
2819 uint32_t Shl = static_cast<uint32_t>(Src0) << (32 - Offset - Width);
2824 return DAG.getConstant(Src0 >> Offset, DL, MVT::i32);
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| /freebsd-13-stable/contrib/llvm-project/llvm/lib/Target/AArch64/ |
| H A D | AArch64FastISel.cpp | 4692 const Value *Src0 = I->getOperand(0); local
4694 if (const auto *C = dyn_cast<ConstantInt>(Src0))
4696 std::swap(Src0, Src1);
4704 if (const auto *ZExt = dyn_cast<ZExtInst>(Src0)) {
4710 Src0 = ZExt->getOperand(0);
4713 } else if (const auto *SExt = dyn_cast<SExtInst>(Src0)) {
4719 Src0 = SExt->getOperand(0);
4724 unsigned Src0Reg = getRegForValue(Src0);
4727 bool Src0IsKill = hasTrivialKill(Src0);
4957 // (Src0 <
[all...] |
| /freebsd-13-stable/contrib/llvm-project/llvm/lib/CodeGen/SelectionDAG/ |
| H A D | SelectionDAGBuilder.cpp | 4192 auto getMaskedStoreOps = [&](Value *&Ptr, Value *&Mask, Value *&Src0,
4194 // llvm.masked.store.*(Src0, Ptr, alignment, Mask)
4195 Src0 = I.getArgOperand(0);
4200 auto getCompressingStoreOps = [&](Value *&Ptr, Value *&Mask, Value *&Src0,
4202 // llvm.masked.compressstore.*(Src0, Ptr, Mask)
4203 Src0 = I.getArgOperand(0);
4217 SDValue Src0 = getValue(Src0Operand); local
4221 EVT VT = Src0.getValueType();
4234 DAG.getMaskedStore(getMemoryRoot(), sdl, Src0, Ptr, Offset, Mask, VT, MMO,
4306 // llvm.masked.scatter.*(Src0, Ptr
4308 SDValue Src0 = getValue(I.getArgOperand(0)); local
4373 SDValue Src0 = getValue(Src0Operand); local
4416 SDValue Src0 = getValue(I.getArgOperand(3)); local
[all...] |
| H A D | LegalizeVectorTypes.cpp | 2075 SDValue Src0 = N->getOperand(1); local
2077 EVT Src0VT = Src0.getValueType();
2091 std::tie(LoOp0, HiOp0) = DAG.SplitVector(Src0, DL);
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| H A D | DAGCombiner.cpp | 20763 SDValue Src0 = DAG.getSplatSourceVector(N0, Index0); local
20765 if (!Src0 || !Src1 || Index0 != Index1 ||
20766 Src0.getValueType().getVectorElementType() != EltVT ||
20774 SDValue X = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, EltVT, Src0, IndexC);
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| /freebsd-13-stable/contrib/llvm-project/llvm/lib/Target/AMDGPU/AsmParser/ |
| H A D | AMDGPUAsmParser.cpp | 3162 const MCOperand &Src0 = Inst.getOperand(Src0Idx); local
3163 if (!Src0.isReg())
3166 auto Reg = Src0.getReg();
3181 const MCOperand &Src0 = Inst.getOperand(Src0Idx); local
3182 if (!Src0.isReg())
3185 auto Reg = Src0.getReg();
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| /freebsd-13-stable/contrib/llvm-project/llvm/include/llvm/CodeGen/ |
| H A D | SelectionDAG.h | 1310 SDValue Offset, SDValue Mask, SDValue Src0, EVT MemVT,
|
| /freebsd-13-stable/contrib/llvm-project/llvm/lib/Target/X86/ |
| H A D | X86ISelLowering.cpp | [all...] |