Searched refs:SCC (Results 26 - 50 of 53) sorted by relevance

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/freebsd-13-stable/contrib/llvm-project/llvm/lib/Transforms/IPO/
H A DInliner.cpp156 // When processing our SCC, check to see if the call site was inlined from
168 if (InlineHistory != -1) // Only do merging for top-level call sites in SCC.
198 // function in this SCC.
302 bool LegacyInlinerBase::runOnSCC(CallGraphSCC &SCC) { argument
303 if (skipSCC(SCC))
305 return inlineCalls(SCC);
309 inlineCallsImpl(CallGraphSCC &SCC, CallGraph &CG, argument
318 LLVM_DEBUG(dbgs() << "Inliner visiting SCC:");
319 for (CallGraphNode *Node : SCC) {
337 for (CallGraphNode *Node : SCC) {
544 inlineCalls(CallGraphSCC &SCC) argument
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H A DArgumentPromotion.cpp1018 PreservedAnalyses ArgumentPromotionPass::run(LazyCallGraph::SCC &C,
1024 // Iterate until we stop promoting from this SCC.
1085 bool runOnSCC(CallGraphSCC &SCC) override;
1114 bool ArgPromotion::runOnSCC(CallGraphSCC &SCC) { argument
1115 if (skipSCC(SCC))
1126 // Iterate until we stop promoting from this SCC.
1129 // Attempt to promote arguments from all functions in this SCC.
1130 for (CallGraphNode *OldNode : SCC) {
1158 // And updat ethe SCC we're iterating as well.
1159 SCC
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H A DFunctionAttrs.cpp101 /// where SCCNodes is the current SCC.
136 // Ignore calls to functions in the same SCC, as long as the call sites
230 /// Deduce readonly/readnone attributes for the SCC.
233 // Check if any of the functions in the SCC read or write memory. If they
260 // If the SCC contains both functions that read and functions that write, then
265 // Success! Functions in this SCC do not access memory, or only read memory.
315 /// in the same SCC that the pointer data flows into. We use this to build an
316 /// SCC of the arguments.
354 /// This tracker checks whether callees are in the SCC, and if so it does not
390 // use. In this case it does not matter if the callee is within our SCC
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H A DAttributor.cpp1123 // Do not modify call instructions outside the SCC.
2108 PreservedAnalyses AttributorCGSCCPass::run(LazyCallGraph::SCC &C,
2173 bool runOnSCC(CallGraphSCC &SCC) override {
2174 if (skipSCC(SCC))
2178 for (CallGraphNode *CGN : SCC)
2187 CallGraph &CG = const_cast<CallGraph &>(SCC.getCallGraph());
2188 CGUpdater.initialize(CG, SCC);
/freebsd-13-stable/contrib/llvm-project/llvm/lib/Target/AMDGPU/
H A DSIOptimizeExecMaskingPreRA.cpp172 assert(AndSCC.getReg() == AMDGPU::SCC);
174 assert(Andn2SCC.getReg() == AMDGPU::SCC);
227 RecalcRegs.insert(AMDGPU::SCC);
H A DAMDGPUPerfHintAnalysis.cpp367 bool AMDGPUPerfHintAnalysis::runOnSCC(CallGraphSCC &SCC) {
375 for (CallGraphNode *I : SCC) {
H A DSIWholeQuadMode.cpp534 .addReg(AMDGPU::SCC);
536 BuildMI(MBB, Before, DebugLoc(), TII->get(AMDGPU::COPY), AMDGPU::SCC)
548 // instructions we want to add necessarily clobber SCC.
555 LiveRange &LR = LIS->getRegUnit(*MCRegUnitIterator(AMDGPU::SCC, TRI));
932 // Physical registers like SCC aren't tracked by default anyway, so just
935 LIS->removeRegUnit(*MCRegUnitIterator(AMDGPU::SCC, TRI));
H A DSIPreEmitPeephole.cpp139 if (!ReadsCond && A->registerDefIsDead(AMDGPU::SCC) &&
H A DSILowerControlFlow.cpp160 assert(ImpDefSCC.getReg() == AMDGPU::SCC && ImpDefSCC.isDef());
209 assert(ImpDefSCC.getReg() == AMDGPU::SCC && ImpDefSCC.isDef());
H A DAMDGPUInstructionSelector.cpp131 if (SrcReg == AMDGPU::SCC) {
302 I.addOperand(MachineOperand::CreateReg(AMDGPU::SCC, true, // isDef
319 // TODO: Should this allow an SCC bank result, and produce a copy from SCC for
325 I.addOperand(MachineOperand::CreateReg(AMDGPU::SCC, true, // isDef
464 BuildMI(*BB, &I, DL, TII.get(AMDGPU::COPY), AMDGPU::SCC)
475 .addReg(AMDGPU::SCC);
993 .addReg(AMDGPU::SCC);
1638 MachineInstr *CopySCC = BuildMI(*BB, &I, DL, TII.get(AMDGPU::COPY), AMDGPU::SCC)
2021 // SCC, th
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H A DSIInstrInfo.cpp574 if (SrcReg == AMDGPU::SCC) {
607 if (SrcReg == AMDGPU::SCC) {
639 if (DestReg == AMDGPU::SCC) {
640 // Copying 64-bit or 32-bit sources to SCC barely makes sense,
5417 // Remove any references to SCC. Vector instructions can't read from it, and
5422 if (Op.isReg() && Op.getReg() == AMDGPU::SCC) {
5423 // Only propagate through live-def of SCC.
5528 assert(Inst.getOperand(3).getReg() == AMDGPU::SCC);
5558 // Find SCC def, and if that is a copy (SCC
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H A DSILowerI1Copies.cpp781 if (MO.isReg() && MO.getReg() == AMDGPU::SCC) {
791 /// for lane mask calculation. Take terminators and SCC into account.
816 llvm_unreachable("SCC used by terminator but no def in block");
H A DAMDGPUAsmPrinter.cpp730 case AMDGPU::SCC:
936 // We force CodeGen to run in SCC order, so the callee's register
/freebsd-13-stable/contrib/llvm-project/llvm/lib/Analysis/
H A DDependenceGraphBuilder.cpp97 // 1. Identify SCCs and for each SCC create a pi-block node containing all
98 // the nodes in that SCC.
99 // 2. Identify incoming edges incident to the nodes inside of the SCC and
101 // 3. Identify outgoing edges from the nodes inside of the SCC to nodes
103 // SCC node instead.
105 // Adding nodes as we iterate through the SCCs cause the SCC
107 // collect a list of nodes that are part of an SCC, and then iterate over
109 // list of nodes in an SCC. Note: trivial SCCs containing a single node are
112 for (auto &SCC : make_range(scc_begin(&Graph), scc_end(&Graph))) {
113 if (SCC
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H A DDDG.cpp192 for (auto &SCC : make_range(scc_begin(&F), scc_end(&F)))
193 for (BasicBlock * BB : SCC)
H A DBlockFrequencyInfoImpl.cpp700 const std::vector<const IrreducibleGraph::IrrNode *> &SCC,
702 // Map from nodes in the SCC to whether it's an entry block.
706 for (const auto *I : SCC)
769 const std::vector<const IrreducibleGraph::IrrNode *> &SCC) {
770 // Translate the SCC into RPO.
775 findIrreducibleHeaders(BFI, G, SCC, Headers, Others);
799 // Translate the SCC into RPO.
697 findIrreducibleHeaders( const BlockFrequencyInfoImplBase &BFI, const IrreducibleGraph &G, const std::vector<const IrreducibleGraph::IrrNode *> &SCC, LoopData::NodeList &Headers, LoopData::NodeList &Others) argument
766 createIrreducibleLoop( BlockFrequencyInfoImplBase &BFI, const IrreducibleGraph &G, LoopData *OuterLoop, std::list<LoopData>::iterator Insert, const std::vector<const IrreducibleGraph::IrrNode *> &SCC) argument
/freebsd-13-stable/contrib/llvm-project/llvm/lib/Transforms/Coroutines/
H A DCoroSplit.cpp16 // add them to the current SCC and restart the IPO pipeline to optimize the
1460 CallGraph &CG, CallGraphSCC &SCC) {
1467 // Update call graph and add the functions we created to the SCC.
1468 coro::updateCallGraph(F, Clones, CG, SCC);
1473 const SmallVectorImpl<Function *> &Clones, LazyCallGraph::SCC &C,
1488 // 'f.cleanup' into the same SCC as the coroutine 'f' they were outlined from,
1498 // above, by inserting the funclets into the same SCC as the corutine, that
1543 // SCC.
1544 static void createDevirtTriggerFunc(CallGraph &CG, CallGraphSCC &SCC) { argument
1561 SmallVector<CallGraphNode *, 8> Nodes(SCC
1458 updateCallGraphAfterCoroutineSplit(Function &F, const coro::Shape &Shape, const SmallVectorImpl<Function *> &Clones, CallGraph &CG, CallGraphSCC &SCC) argument
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H A DCoroutines.cpp206 // NewFuncs. Builds CGNs for the NewFuncs and adds them to the current SCC.
208 CallGraph &CG, CallGraphSCC &SCC) {
214 SmallVector<CallGraphNode *, 8> Nodes(SCC.begin(), SCC.end());
222 SCC.initialize(Nodes);
207 updateCallGraph(Function &ParentFunc, ArrayRef<Function *> NewFuncs, CallGraph &CG, CallGraphSCC &SCC) argument
H A DCoroInternal.h36 // adds coroutine subfunctions to the SCC to be processed by IPO pipeline.
52 CallGraph &CG, CallGraphSCC &SCC);
/freebsd-13-stable/contrib/llvm-project/llvm/lib/Transforms/Scalar/
H A DStructurizeCFG.cpp385 auto &SCC = *SCCI; local
387 // An SCC up to the size of 2, can be reduced to an entry (the last node),
390 unsigned Size = SCC.size();
394 // Add the SCC nodes to the Order array.
395 for (auto &N : SCC) {
396 assert(I < E && "SCC size mismatch!");
400 assert(I == E && "SCC size mismatch!");
408 // Collect the set of nodes in the SCC's subgraph. These are only the
410 // will have the same exact SCC all over again.
H A DNewGVN.cpp22 /// "SCC based value numbering" by L. Taylor Simpson) with one major difference:
181 // Tarjan's SCC finding algorithm with Nuutila's improvements
183 // It also wants to hand us SCC's that are unrelated to the phi node we ask
186 // This SCC finder is specialized to walk use-def chains, and only follows
251 // of SCC's, but not individual member order
1711 // In order to compute cycle-freeness, we do SCC finding on the instruction,
1712 // and see what kind of SCC it ends up in. If it is a singleton, it is
1719 auto &SCC = SCCFinder.getComponentFor(I);
1720 // It's cycle free if it's size 1 or the SCC is *only* phi nodes.
1721 if (SCC
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/freebsd-13-stable/contrib/llvm-project/llvm/lib/CodeGen/SelectionDAG/
H A DDAGCombiner.cpp9408 if (SDValue SCC = SimplifySetCC(getSetCCResultType(N0.getValueType()), N0, N1,
9410 AddToWorklist(SCC.getNode());
9412 if (ConstantSDNode *SCCC = dyn_cast<ConstantSDNode>(SCC.getNode())) {
9417 } else if (SCC->isUndef()) {
9421 } else if (SCC.getOpcode() == ISD::SETCC) {
9424 ISD::SELECT_CC, SDLoc(N), N2.getValueType(), SCC.getOperand(0),
9425 SCC.getOperand(1), N2, N3, SCC.getOperand(2));
9426 SelectOp->setFlags(SCC->getFlags());
10198 if (SDValue SCC
20928 SDValue SCC = SimplifySelectCC(DL, N0.getOperand(0), N0.getOperand(1), N1, N2, local
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/freebsd-13-stable/contrib/llvm-project/llvm/lib/Passes/
H A DPassBuilder.cpp325 PreservedAnalyses run(LazyCallGraph::SCC &C, CGSCCAnalysisManager &,
339 Result run(LazyCallGraph::SCC &, CGSCCAnalysisManager &, LazyCallGraph &G) {
2289 LazyCallGraph::SCC, CGSCCAnalysisManager, LazyCallGraph &, \
/freebsd-13-stable/contrib/llvm-project/llvm/lib/Target/AMDGPU/Utils/
H A DAMDGPUBaseInfo.cpp1003 Reg == AMDGPU::SCC;
/freebsd-13-stable/contrib/llvm-project/llvm/lib/Target/AMDGPU/MCTargetDesc/
H A DAMDGPUInstPrinter.cpp320 case AMDGPU::SCC:

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