Searched refs:MIB (Results 26 - 50 of 134) sorted by relevance

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/freebsd-13-stable/contrib/llvm-project/llvm/lib/CodeGen/SelectionDAG/
H A DInstrEmitter.h48 MachineInstrBuilder &MIB,
61 void AddRegisterOperand(MachineInstrBuilder &MIB,
72 void AddOperand(MachineInstrBuilder &MIB,
/freebsd-13-stable/contrib/llvm-project/llvm/lib/Target/AArch64/GISel/
H A DAArch64InstructionSelector.cpp105 MachineIRBuilder &MIB) const;
196 MachineIRBuilder &MIB) const;
299 MachineIRBuilder &MIB) const;
303 void renderTruncImm(MachineInstrBuilder &MIB, const MachineInstr &MI,
305 void renderLogicalImm32(MachineInstrBuilder &MIB, const MachineInstr &I,
307 void renderLogicalImm64(MachineInstrBuilder &MIB, const MachineInstr &I,
322 MachineIRBuilder &MIB) const;
325 MachineIRBuilder &MIB) const;
706 MachineIRBuilder MIB(I);
708 MIB
1516 auto MIB = local
1895 auto MIB = BuildMI(MBB, I, I.getDebugLoc(), TII.get(AArch64::TBNZW)) local
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/freebsd-13-stable/contrib/llvm-project/llvm/lib/Target/Mips/
H A DMips16InstrInfo.cpp90 MachineInstrBuilder MIB = BuildMI(MBB, I, DL, get(Opc)); local
93 MIB.addReg(DestReg, RegState::Define);
96 MIB.addReg(SrcReg, getKillRegState(KillSrc));
184 static void addSaveRestoreRegs(MachineInstrBuilder &MIB, argument
198 MIB.addReg(Reg, Flags);
218 MachineInstrBuilder MIB; local
220 MIB = BuildMI(MBB, I, DL, get(Opc));
222 addSaveRestoreRegs(MIB, CSI);
224 MIB.addReg(Mips::S2);
226 MIB
248 MachineInstrBuilder MIB; local
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H A DMicroMipsSizeReduction.cpp711 MachineInstrBuilder MIB = BuildMI(MBB, MI, dl, NewMCID); local
714 MIB.add(MI->getOperand(2));
717 MIB.add(MI->getOperand(0));
718 MIB.add(MI->getOperand(2));
723 MIB.add(MI->getOperand(0));
724 MIB.add(MI->getOperand(1));
725 MIB.add(MI->getOperand(2));
727 MIB.add(MI->getOperand(0));
728 MIB.add(MI->getOperand(2));
729 MIB
755 << " to: " << *MIB); local
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H A DMipsCallLowering.cpp123 MachineInstrBuilder &MIB)
124 : IncomingValueHandler(MIRBuilder, MRI), MIB(MIB) {}
128 MIB.addDef(PhysReg, RegState::Implicit);
131 MachineInstrBuilder &MIB; member in class:__anon4215::CallReturnHandler
215 MachineInstrBuilder &MIB)
216 : MipsHandler(MIRBuilder, MRI), MIB(MIB) {}
233 MachineInstrBuilder &MIB; member in class:__anon4216::OutgoingValueHandler
253 MIB
122 CallReturnHandler(MachineIRBuilder &MIRBuilder, MachineRegisterInfo &MRI, MachineInstrBuilder &MIB) argument
214 OutgoingValueHandler(MachineIRBuilder &MIRBuilder, MachineRegisterInfo &MRI, MachineInstrBuilder &MIB) argument
530 MachineInstrBuilder MIB = MIRBuilder.buildInstrNoInsert( local
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H A DMipsInstrInfo.cpp111 MachineInstrBuilder MIB = BuildMI(&MBB, DL, MCID); local
116 MIB.add(Cond[i]);
118 MIB.addMBB(TBB);
597 MachineInstrBuilder MIB; local
639 MIB = BuildMI(*I->getParent(), I, I->getDebugLoc(), get(NewOpc));
649 MIB->RemoveOperand(0);
652 MIB.add(I->getOperand(J));
655 MIB.addImm(0);
663 MIB.addSym(MO.getMCSymbol(), MipsII::MO_JALR);
672 MIB
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/freebsd-13-stable/contrib/llvm-project/llvm/lib/CodeGen/
H A DPatchableFunction.cpp82 auto MIB = BuildMI(FirstMBB, FirstActualI, FirstActualI->getDebugLoc(), local
88 MIB.add(MO);
H A DFixupStatepointCallerSaved.cpp220 MachineInstrBuilder MIB(MF, NewMI);
230 MIB.addImm(StackMaps::IndirectMemRefOp);
231 MIB.addImm(getRegisterSize(TRI, MO.getReg()));
234 MIB.addFrameIndex(FI);
235 MIB.addImm(0);
238 MIB.add(MO);
H A DMachineInstrBundle.cpp135 MachineInstrBuilder MIB = local
137 Bundle.prepend(MIB);
216 MIB.addReg(Reg, getDefRegState(true) | getDeadRegState(isDead) |
225 MIB.addReg(Reg, getKillRegState(isKill) | getUndefRegState(isUndef) |
233 MIB.setMIFlag(MachineInstr::FrameSetup);
235 MIB.setMIFlag(MachineInstr::FrameDestroy);
/freebsd-13-stable/contrib/llvm-project/llvm/lib/CodeGen/GlobalISel/
H A DCombinerHelper.cpp591 MachineIRBuilder MIB(MI);
592 MIB.buildCopy(MI.getOperand(0).getReg(), MI.getOperand(1).getReg());
775 auto MIB = MIRBuilder.buildInstr(NewOpcode); local
777 MIB.addDef(MatchInfo.Addr);
778 MIB.addUse(MI.getOperand(0).getReg());
780 MIB.addDef(MI.getOperand(0).getReg());
781 MIB.addDef(MatchInfo.Addr);
784 MIB.addUse(MatchInfo.Base);
785 MIB.addUse(MatchInfo.Offset);
786 MIB
944 getMemsetValue(Register Val, LLT Ty, MachineIRBuilder &MIB) argument
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H A DIRTranslator.cpp425 bool IRTranslator::translateSwitch(const User &U, MachineIRBuilder &MIB) { argument
455 MIB.buildBr(*DefaultMBB);
491 if (!lowerSwitchWorkItem(W, SI.getCondition(), SwitchMBB, DefaultMBB, MIB))
501 MachineIRBuilder MIB(*MBB->getParent());
502 MIB.setMBB(*MBB);
503 MIB.setDebugLoc(CurBuilder->getDebugLoc());
508 auto Table = MIB.buildJumpTable(PtrTy, JT.JTI);
509 MIB.buildBrJT(Table.getReg(0), JT.JTI, JT.Reg);
515 MachineIRBuilder MIB(*HeaderBB->getParent());
516 MIB
556 emitSwitchCase(SwitchCG::CaseBlock &CB, MachineBasicBlock *SwitchBB, MachineIRBuilder &MIB) argument
631 lowerJumpTableWorkItem(SwitchCG::SwitchWorkListItem W, MachineBasicBlock *SwitchMBB, MachineBasicBlock *CurMBB, MachineBasicBlock *DefaultMBB, MachineIRBuilder &MIB, MachineFunction::iterator BBI, BranchProbability UnhandledProbs, SwitchCG::CaseClusterIt I, MachineBasicBlock *Fallthrough, bool FallthroughUnreachable) argument
703 lowerSwitchRangeWorkItem(SwitchCG::CaseClusterIt I, Value *Cond, MachineBasicBlock *Fallthrough, bool FallthroughUnreachable, BranchProbability UnhandledProbs, MachineBasicBlock *CurMBB, MachineIRBuilder &MIB, MachineBasicBlock *SwitchMBB) argument
737 lowerSwitchWorkItem(SwitchCG::SwitchWorkListItem W, Value *Cond, MachineBasicBlock *SwitchMBB, MachineBasicBlock *DefaultMBB, MachineIRBuilder &MIB) argument
1190 auto MIB = local
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/freebsd-13-stable/contrib/llvm-project/llvm/lib/Target/ARM/
H A DARMBaseInstrInfo.cpp802 MachineInstrBuilder MIB = local
808 MIB.addImm(0x800);
810 MIB.add(predOps(ARMCC::AL))
822 MachineInstrBuilder MIB = BuildMI(MBB, I, I->getDebugLoc(), get(Opc)); local
825 MIB.addImm(0x800);
827 MIB.addImm(8);
829 MIB.addReg(SrcReg, getKillRegState(KillSrc))
834 void llvm::addUnpredicatedMveVpredNOp(MachineInstrBuilder &MIB) { argument
835 MIB.addImm(ARMVCC::None);
836 MIB
839 addUnpredicatedMveVpredROp(MachineInstrBuilder &MIB, Register DestReg) argument
845 addPredicatedMveVpredNOp(MachineInstrBuilder &MIB, unsigned Cond) argument
850 addPredicatedMveVpredROp(MachineInstrBuilder &MIB, unsigned Cond, unsigned Inactive) argument
887 MachineInstrBuilder MIB = BuildMI(MBB, I, DL, get(Opc), DestReg); local
1069 AddDReg(MachineInstrBuilder &MIB, unsigned Reg, unsigned SubIdx, unsigned State, const TargetRegisterInfo *TRI) const argument
1140 MachineInstrBuilder MIB = BuildMI(MBB, I, DebugLoc(), get(ARM::STRD)); local
1148 MachineInstrBuilder MIB = BuildMI(MBB, I, DebugLoc(), get(ARM::STMIA)) local
1177 auto MIB = BuildMI(MBB, I, DebugLoc(), get(ARM::MVE_VSTRWU32)); local
1198 MachineInstrBuilder MIB = BuildMI(MBB, I, DebugLoc(), local
1223 MachineInstrBuilder MIB = BuildMI(MBB, I, DebugLoc(), local
1238 MachineInstrBuilder MIB = BuildMI(MBB, I, DebugLoc(), get(ARM::VSTMDIA)) local
1376 MachineInstrBuilder MIB; local
1416 auto MIB = BuildMI(MBB, I, DL, get(ARM::MVE_VLDRWU32), DestReg); local
1434 MachineInstrBuilder MIB = BuildMI(MBB, I, DL, get(ARM::VLDMDIA)) local
1457 MachineInstrBuilder MIB = BuildMI(MBB, I, DL, get(ARM::VLDMDIA)) local
1473 MachineInstrBuilder MIB = BuildMI(MBB, I, DL, get(ARM::VLDMDIA)) local
4835 MachineInstrBuilder MIB; local
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H A DARMInstrInfo.cpp121 MachineInstrBuilder MIB; local
123 MIB = BuildMI(MBB, MI, DL, get(ARM::MOV_ga_pcrel_ldr), Reg)
130 MIB.addMemOperand(MMO);
H A DARMFastISel.cpp238 const MachineInstrBuilder &AddOptionalDefs(const MachineInstrBuilder &MIB);
240 const MachineInstrBuilder &MIB,
283 ARMFastISel::AddOptionalDefs(const MachineInstrBuilder &MIB) { argument
284 MachineInstr *MI = &*MIB;
290 MIB.add(predOps(ARMCC::AL));
296 MIB.add(CPSR ? t1CondCodeOp() : condCodeOp());
297 return MIB;
578 MachineInstrBuilder MIB; local
581 MIB = BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(Opc),
584 MIB
599 MachineInstrBuilder MIB = BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, local
610 MachineInstrBuilder MIB; local
857 AddLoadStoreOperands(MVT VT, Address &Addr, const MachineInstrBuilder &MIB, MachineMemOperand::Flags Flags, bool useAM3) argument
990 MachineInstrBuilder MIB = BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, local
1128 MachineInstrBuilder MIB = BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, local
1438 MachineInstrBuilder MIB; local
2166 MachineInstrBuilder MIB = BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, local
2262 MachineInstrBuilder MIB = BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, local
2401 MachineInstrBuilder MIB = BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, local
2720 MachineInstrBuilder MIB = BuildMI( local
2967 MachineInstrBuilder MIB = local
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H A DMLxExpansionPass.cpp290 MachineInstrBuilder MIB = BuildMI(MBB, MI, MI->getDebugLoc(), MCID1, TmpReg) local
294 MIB.addImm(LaneImm);
295 MIB.addImm(Pred).addReg(PredReg);
297 MIB = BuildMI(MBB, MI, MI->getDebugLoc(), MCID2)
302 MIB.addReg(TmpReg, getKillRegState(true))
305 MIB.addReg(AccReg).addReg(TmpReg, getKillRegState(true));
307 MIB.addImm(Pred).addReg(PredReg);
H A DThumb2InstrInfo.cpp167 MachineInstrBuilder MIB = BuildMI(MBB, I, DL, get(ARM::t2STRDi8)); local
168 AddDReg(MIB, SrcReg, ARM::gsub_0, getKillRegState(isKill), TRI);
169 AddDReg(MIB, SrcReg, ARM::gsub_1, 0, TRI);
170 MIB.addFrameIndex(FI).addImm(0).addMemOperand(MMO).add(predOps(ARMCC::AL));
208 MachineInstrBuilder MIB = BuildMI(MBB, I, DL, get(ARM::t2LDRDi8)); local
209 AddDReg(MIB, DestReg, ARM::gsub_0, RegState::DefineNoRead, TRI);
210 AddDReg(MIB, DestReg, ARM::gsub_1, RegState::DefineNoRead, TRI);
211 MIB.addFrameIndex(FI).addImm(0).addMemOperand(MMO).add(predOps(ARMCC::AL));
214 MIB.addReg(DestReg, RegState::ImplicitDefine);
348 MachineInstrBuilder MIB
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/freebsd-13-stable/contrib/llvm-project/llvm/lib/Target/X86/
H A DX86InstrInfo.cpp1287 MachineInstrBuilder MIB = local
1294 MIB.addReg(0).addImm(1ULL << ShAmt)
1300 addRegOffset(MIB, InRegLEA, true, 1);
1304 addRegOffset(MIB, InRegLEA, true, -1);
1312 addRegOffset(MIB, InRegLEA, true, MI.getOperand(2).getImm());
1326 addRegReg(MIB, InRegLEA, true, InRegLEA, false);
1334 BuildMI(*MFI, &*MIB, MI.getDebugLoc(), get(X86::IMPLICIT_DEF), InRegLEA2);
1335 InsMI2 = BuildMI(*MFI, &*MIB, MI.getDebugLoc(), get(TargetOpcode::COPY))
1338 addRegReg(MIB, InRegLEA, true, InRegLEA2, true);
1346 MachineInstr *NewMI = MIB;
1645 MachineInstrBuilder MIB = BuildMI(MF, MI.getDebugLoc(), local
2935 auto MIB = BuildMI(MBB, I, MBB.findDebugLoc(I), get(Opc)); local
4357 Expand2AddrUndef(MachineInstrBuilder &MIB, const MCInstrDesc &Desc) argument
4378 Expand2AddrKreg(MachineInstrBuilder &MIB, const MCInstrDesc &Desc, unsigned Reg) argument
4386 expandMOV32r1(MachineInstrBuilder &MIB, const TargetInstrInfo &TII, bool MinusOne) argument
4404 ExpandMOVImmSExti8(MachineInstrBuilder &MIB, const TargetInstrInfo &TII, const X86Subtarget &Subtarget) argument
4462 expandLoadStackGuard(MachineInstrBuilder &MIB, const TargetInstrInfo &TII) argument
4484 expandXorFP(MachineInstrBuilder &MIB, const TargetInstrInfo &TII) argument
4499 expandNOVLXLoad(MachineInstrBuilder &MIB, const TargetRegisterInfo *TRI, const MCInstrDesc &LoadDesc, const MCInstrDesc &BroadcastDesc, unsigned SubIdx) argument
4522 expandNOVLXStore(MachineInstrBuilder &MIB, const TargetRegisterInfo *TRI, const MCInstrDesc &StoreDesc, const MCInstrDesc &ExtractDesc, unsigned SubIdx) argument
4544 expandSHXDROT(MachineInstrBuilder &MIB, const MCInstrDesc &Desc) argument
5180 addOperands(MachineInstrBuilder &MIB, ArrayRef<MachineOperand> MOs, int PtrOffset = 0) argument
5297 MachineInstrBuilder MIB = BuildMI(*InsertPt->getParent(), InsertPt, local
6196 MachineInstrBuilder MIB = BuildMI(MF, DL, get(Opc), Reg); local
6271 MachineInstrBuilder MIB = BuildMI(MF, DL, get(Opc)); local
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H A DX86ExpandPseudo.cpp245 MachineInstrBuilder MIB = BuildMI(MBB, MBBI, DL, TII->get(Op)); local
247 MIB.addGlobalAddress(JumpTarget.getGlobal(), JumpTarget.getOffset(),
251 MIB.addExternalSymbol(JumpTarget.getSymbolName(),
255 MIB.addImm(MBBI->getOperand(2).getImm());
262 MachineInstrBuilder MIB = BuildMI(MBB, MBBI, DL, TII->get(Op)); local
264 MIB.add(MBBI->getOperand(i));
314 MachineInstrBuilder MIB; local
316 MIB = BuildMI(MBB, MBBI, DL,
319 MIB = BuildMI(MBB, MBBI, DL,
330 MIB
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/freebsd-13-stable/contrib/llvm-project/llvm/lib/Target/Hexagon/
H A DHexagonFixupHwLoops.cpp173 MachineInstrBuilder MIB; local
191 MIB = BuildMI(*MBB, MII, DL, TII->get(newOp));
194 MIB.add(MII->getOperand(i));
/freebsd-13-stable/contrib/llvm-project/llvm/lib/Target/SystemZ/
H A DSystemZElimCompare.cpp230 MachineInstrBuilder MIB(*Branch->getParent()->getParent(), Branch);
231 MIB.add(MI.getOperand(0)).add(MI.getOperand(1)).add(Target);
236 MIB.addReg(SystemZ::CC, RegState::ImplicitDefine | RegState::Dead);
294 auto MIB = BuildMI(*MI.getParent(), MI, MI.getDebugLoc(), TII->get(Opcode));
296 MIB.add(MO);
297 MIB.setMemRefs(MI.memoperands());
303 MIB.setMIFlag(MachineInstr::MIFlag::NoFPExcept);
668 MachineInstrBuilder MIB(*Branch->getParent()->getParent(), Branch);
670 MIB.add(Compare.getOperand(I));
671 MIB
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H A DSystemZFrameLowering.cpp182 // Add GPR64 to the save instruction being built by MIB, which is in basic
186 static void addSavedGPR(MachineBasicBlock &MBB, MachineInstrBuilder &MIB, argument
193 MIB.addReg(GPR64, getImplRegState(IsImplicit) | getKillRegState(!IsLive));
218 MachineInstrBuilder MIB = BuildMI(MBB, MBBI, DL, TII->get(SystemZ::STMG)); local
221 addSavedGPR(MBB, MIB, SpillGPRs.LowGPR, false);
222 addSavedGPR(MBB, MIB, SpillGPRs.HighGPR, false);
225 MIB.addReg(SystemZ::R15D).addImm(SpillGPRs.GPROffset);
232 addSavedGPR(MBB, MIB, Reg, true);
238 addSavedGPR(MBB, MIB, SystemZ::ArgGPRs[I], true);
293 MachineInstrBuilder MIB local
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/freebsd-13-stable/contrib/llvm-project/llvm/lib/Target/NVPTX/
H A DNVPTXPeephole.cpp111 MachineInstrBuilder MIB = local
117 MBB.insert((MachineBasicBlock::iterator)&Root, MIB);
/freebsd-13-stable/usr.sbin/bsnmpd/modules/snmp_hast/
H A DMakefile35 BMIBS= BEGEMOT-HAST-MIB.txt
/freebsd-13-stable/contrib/llvm-project/llvm/lib/Target/WebAssembly/
H A DWebAssemblyFixIrreducibleControlFlow.cpp366 MachineInstrBuilder MIB = local
373 MIB.addReg(Reg);
382 unsigned Index = MIB.getInstr()->getNumExplicitOperands() - 1;
385 MIB.addMBB(Entry);
479 MIB.addMBB(MIB.getInstr()
480 ->getOperand(MIB.getInstr()->getNumExplicitOperands() - 1)
/freebsd-13-stable/lib/libugidfw/
H A Dugidfw.c61 #define MIB "security.mac.bsdextended" macro
1128 error = sysctlbyname(MIB ".rule_version", &version, &len, NULL, 0);
1150 error = sysctlbyname(MIB ".rule_count", &rule_count, &len, NULL, 0);
1157 MIB);
1172 error = sysctlbyname(MIB ".rule_slots", &rule_slots, &len, NULL, 0);
1178 snprintf(errstr, buflen, "Data error in %s.rule_slots", MIB);
1202 error = bsde_get_mib(MIB ".rules", name, &len);
1204 snprintf(errstr, errlen, "%s: %s", MIB ".rules",
1216 snprintf(errstr, errlen, "%s.%d: %s", MIB ".rules",
1221 MIB "
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