Searched refs:MCInst (Results 176 - 200 of 296) sorted by relevance

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/freebsd-13-stable/contrib/llvm-project/llvm/lib/Target/X86/
H A DX86AsmPrinter.h48 void count(MCInst &Inst, const MCSubtargetInfo &STI,
81 void EmitAndCountInstruction(MCInst &Inst);
/freebsd-13-stable/contrib/llvm-project/llvm/lib/MC/MCDisassembler/
H A DDisassembler.cpp19 #include "llvm/MC/MCInst.h"
169 static int getItineraryLatency(LLVMDisasmContext *DC, const MCInst &Inst) {
194 static int getLatency(LLVMDisasmContext *DC, const MCInst &Inst) {
230 static void emitLatency(LLVMDisasmContext *DC, const MCInst &Inst) {
260 MCInst Inst;
H A DMCDisassembler.cpp26 bool MCDisassembler::tryAddingSymbolicOperand(MCInst &Inst, int64_t Value,
/freebsd-13-stable/contrib/llvm-project/llvm/lib/Object/
H A DRecordStreamer.h48 void emitInstruction(const MCInst &Inst, const MCSubtargetInfo &STI) override;
/freebsd-13-stable/contrib/llvm-project/llvm/tools/llvm-mca/Views/
H A DSummaryView.cpp25 SummaryView::SummaryView(const MCSchedModel &Model, ArrayRef<MCInst> S,
H A DTimelineView.cpp21 llvm::ArrayRef<llvm::MCInst> S, unsigned Iterations,
192 for (const MCInst &Inst : Source) {
302 for (const MCInst &Inst : Source) {
H A DInstructionInfoView.cpp40 const MCInst &Inst = Source[I];
/freebsd-13-stable/contrib/llvm-project/llvm/lib/Target/Mips/
H A DMipsMCInstLower.cpp1 //===- MipsMCInstLower.cpp - Convert Mips MachineInstr to MCInst ----------===//
10 // MCInst records.
22 #include "llvm/MC/MCInst.h"
215 lowerLongBranchLUi(const MachineInstr *MI, MCInst &OutMI) const {
253 MCInst &OutMI, int Opcode) const {
295 MCInst &OutMI) const {
315 void MipsMCInstLower::Lower(const MachineInstr *MI, MCInst &OutMI) const {
/freebsd-13-stable/contrib/llvm-project/llvm/lib/Target/Sparc/
H A DSparcMCInstLower.cpp1 //===-- SparcMCInstLower.cpp - Convert Sparc MachineInstr to MCInst -------===//
10 // MCInst records.
24 #include "llvm/MC/MCInst.h"
94 MCInst &OutMI,
/freebsd-13-stable/contrib/llvm-project/llvm/lib/Target/VE/
H A DVEMCInstLower.cpp1 //===-- VEMCInstLower.cpp - Convert VE MachineInstr to MCInst -------------===//
10 // MCInst records.
24 #include "llvm/MC/MCInst.h"
71 void llvm::LowerVEMachineInstrToMCInst(const MachineInstr *MI, MCInst &OutMI,
/freebsd-13-stable/contrib/llvm-project/llvm/lib/Target/WebAssembly/Disassembler/
H A DWebAssemblyDisassembler.cpp23 #include "llvm/MC/MCInst.h"
46 DecodeStatus getInstruction(MCInst &Instr, uint64_t &Size,
100 static bool parseLEBImmediate(MCInst &MI, uint64_t &Size,
110 bool parseImmediate(MCInst &MI, uint64_t &Size, ArrayRef<uint8_t> Bytes) {
160 MCInst &MI, uint64_t &Size, ArrayRef<uint8_t> Bytes, uint64_t /*Address*/,
/freebsd-13-stable/contrib/llvm-project/llvm/lib/Target/Hexagon/MCTargetDesc/
H A DHexagonMCChecker.cpp21 #include "llvm/MC/MCInst.h"
55 MCInst const &Inst = *I.getInst();
66 void HexagonMCChecker::initReg(MCInst const &MCI, unsigned R, unsigned &PredReg,
89 void HexagonMCChecker::init(MCInst const &MCI) {
198 MCSubtargetInfo const &STI, MCInst &mcb,
270 static bool isNeitherAnorX(MCInstrInfo const &MCII, MCInst const &ID) {
288 MCInst const *HasSoloAXInst = nullptr;
335 SmallVector<MCInst const *, 2> BranchLocations;
342 MCInst const &I = *BranchLocations[J];
372 MCInst cons
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H A DHexagonMCCodeEmitter.cpp19 #include "llvm/MC/MCInst.h"
340 uint32_t HexagonMCCodeEmitter::parseBits(size_t Last, MCInst const &MCB,
341 MCInst const &MCI) const {
367 void HexagonMCCodeEmitter::encodeInstruction(const MCInst &MI, raw_ostream &OS,
370 MCInst &HMB = const_cast<MCInst &>(MI);
382 MCInst &HMI = const_cast<MCInst &>(*I.getInst());
400 void HexagonMCCodeEmitter::EncodeSingleInstruction(const MCInst &MI,
435 const MCInst *Sub
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H A DHexagonMCDuplexInfo.cpp189 unsigned HexagonMCInstrInfo::getDuplexCandidateGroup(MCInst const &MCI) {
539 bool HexagonMCInstrInfo::subInstWouldBeExtended(MCInst const &potentialDuplex) {
577 MCInst const &MIa, bool ExtendedA,
578 MCInst const &MIb, bool ExtendedB,
599 MCInst SubInst0 = HexagonMCInstrInfo::deriveSubInst(MIa);
600 MCInst SubInst1 = HexagonMCInstrInfo::deriveSubInst(MIb);
655 bool HexagonMCInstrInfo::isDuplexPair(MCInst const &MIa, MCInst const &MIb) {
661 inline static void addOps(MCInst &subInstPtr, MCInst cons
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/freebsd-13-stable/contrib/llvm-project/llvm/include/llvm/MC/
H A DMCInstrDesc.h23 class MCInst;
315 bool mayAffectControlFlow(const MCInst &MI, const MCRegisterInfo &RI) const;
624 bool hasDefOfPhysReg(const MCInst &MI, unsigned Reg,
/freebsd-13-stable/contrib/llvm-project/llvm/lib/Target/WebAssembly/MCTargetDesc/
H A DWebAssemblyMCCodeEmitter.cpp20 #include "llvm/MC/MCInst.h"
42 uint64_t getBinaryCodeForInstr(const MCInst &MI,
46 void encodeInstruction(const MCInst &MI, raw_ostream &OS,
60 const MCInst &MI, raw_ostream &OS, SmallVectorImpl<MCFixup> &Fixups,
73 // For br_table instructions, encode the size of the table. In the MCInst,
/freebsd-13-stable/contrib/llvm-project/llvm/lib/Target/X86/AsmParser/
H A DX86Operand.h18 #include "llvm/MC/MCInst.h"
509 void addExpr(MCInst &Inst, const MCExpr *Expr) const {
517 void addRegOperands(MCInst &Inst, unsigned N) const {
522 void addGR32orGR64Operands(MCInst &Inst, unsigned N) const {
530 void addGR16orGR32orGR64Operands(MCInst &Inst, unsigned N) const {
539 void addAVX512RCOperands(MCInst &Inst, unsigned N) const {
544 void addImmOperands(MCInst &Inst, unsigned N) const {
549 void addMaskPairOperands(MCInst &Inst, unsigned N) const {
573 void addMemOperands(MCInst &Inst, unsigned N) const {
585 void addAbsMemOperands(MCInst
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/freebsd-13-stable/contrib/llvm-project/llvm/lib/Target/VE/AsmParser/
H A DVEAsmParser.cpp1 //===-- VEAsmParser.cpp - Parse VE assembly to MCInst instructions --------===//
19 #include "llvm/MC/MCInst.h"
448 void addRegOperands(MCInst &Inst, unsigned N) const {
453 void addImmOperands(MCInst &Inst, unsigned N) const {
459 void addZeroOperands(MCInst &Inst, unsigned N) const {
463 void addUImm0to2Operands(MCInst &Inst, unsigned N) const {
467 void addUImm1Operands(MCInst &Inst, unsigned N) const {
471 void addUImm2Operands(MCInst &Inst, unsigned N) const {
475 void addUImm3Operands(MCInst &Inst, unsigned N) const {
479 void addUImm6Operands(MCInst
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/freebsd-13-stable/contrib/llvm-project/llvm/lib/Target/Hexagon/AsmParser/
H A DHexagonAsmParser.cpp1 //===-- HexagonAsmParser.cpp - Parse Hexagon asm to MCInst instructions----===//
30 #include "llvm/MC/MCInst.h"
95 MCInst MCB;
128 void canonicalizeImmediates(MCInst &MCI);
129 bool matchOneInstruction(MCInst &MCB, SMLoc IDLoc,
141 int processInstruction(MCInst &Inst, OperandVector const &Operands,
382 void addRegOperands(MCInst &Inst, unsigned N) const {
387 void addImmOperands(MCInst &Inst, unsigned N) const {
392 void addSignedImmOperands(MCInst &Inst, unsigned N) const {
411 void addn1ConstOperands(MCInst
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/freebsd-13-stable/contrib/llvm-project/llvm/lib/Target/RISCV/AsmParser/
H A DRISCVAsmParser.cpp1 //===-- RISCVAsmParser.cpp - Parse RISCV assembly to MCInst instructions --===//
27 #include "llvm/MC/MCInst.h"
98 void emitToStreamer(MCStreamer &S, const MCInst &Inst);
111 void emitLoadLocalAddress(MCInst &Inst, SMLoc IDLoc, MCStreamer &Out);
114 void emitLoadAddress(MCInst &Inst, SMLoc IDLoc, MCStreamer &Out);
118 void emitLoadTLSIEAddress(MCInst &Inst, SMLoc IDLoc, MCStreamer &Out);
122 void emitLoadTLSGDAddress(MCInst &Inst, SMLoc IDLoc, MCStreamer &Out);
125 void emitLoadStoreSymbol(MCInst &Inst, unsigned Opcode, SMLoc IDLoc,
132 bool checkPseudoAddTPRel(MCInst &Inst, OperandVector &Operands);
135 bool validateInstruction(MCInst
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/freebsd-13-stable/contrib/llvm-project/llvm/lib/Target/AArch64/AsmParser/
H A DAArch64AsmParser.cpp1 //==- AArch64AsmParser.cpp - Parse AArch64 assembly to MCInst instructions -==//
28 #include "llvm/MC/MCInst.h"
86 static PrefixInfo CreateFromInst(const MCInst &Inst, uint64_t TSFlags) {
184 bool validateInstruction(MCInst &Inst, SMLoc &IDLoc,
1424 void addExpr(MCInst &Inst, const MCExpr *Expr) const {
1434 void addRegOperands(MCInst &Inst, unsigned N) const {
1439 void addGPR32as64Operands(MCInst &Inst, unsigned N) const {
1451 void addGPR64as32Operands(MCInst &Inst, unsigned N) const {
1464 void addFPRasZPRRegOperands(MCInst &Inst, unsigned N) const {
1478 void addVectorReg64Operands(MCInst
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/freebsd-13-stable/contrib/llvm-project/llvm/include/llvm/MC/MCParser/
H A DMCTargetAsmParser.h26 class MCInst;
391 /// construct the appropriate MCInst, or emit an error. On success, the entire
420 /// instruction as an actual MCInst and emit it to the specified MCStreamer.
445 checkEarlyTargetMatchPredicate(MCInst &Inst, const OperandVector &Operands) {
451 virtual unsigned checkTargetMatchPredicate(MCInst &Inst) {
/freebsd-13-stable/contrib/llvm-project/llvm/tools/llvm-mca/
H A DCodeRegion.cpp109 void CodeRegions::addInstruction(const MCInst &Instruction) {
/freebsd-13-stable/contrib/llvm-project/llvm/lib/Target/AVR/
H A DAVRMCInstLower.cpp1 //===-- AVRMCInstLower.cpp - Convert AVR MachineInstr to an MCInst --------===//
10 // MCInst records.
21 #include "llvm/MC/MCInst.h"
62 void AVRMCInstLower::lowerInstruction(const MachineInstr &MI, MCInst &OutMI) const {
/freebsd-13-stable/contrib/llvm-project/llvm/lib/Target/BPF/AsmParser/
H A DBPFAsmParser.cpp1 //===-- BPFAsmParser.cpp - Parse BPF assembly to MCInst instructions --===//
15 #include "llvm/MC/MCInst.h"
178 void addExpr(MCInst &Inst, const MCExpr *Expr) const {
188 void addRegOperands(MCInst &Inst, unsigned N) const {
193 void addImmOperands(MCInst &Inst, unsigned N) const {
289 MCInst Inst;

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