Searched refs:Instr (Results 26 - 50 of 93) sorted by relevance

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/freebsd-13-stable/contrib/llvm-project/llvm/include/llvm/CodeGen/
H A DReachingDefAnalysis.h47 ReachingDef(int Instr) : Encoded(((uintptr_t) Instr << 2) | 2) {} argument
H A DLiveIntervals.h221 bool isNotInMIMap(const MachineInstr &Instr) const {
222 return !Indexes->hasIndex(Instr);
226 SlotIndex getInstructionIndex(const MachineInstr &Instr) const {
227 return Indexes->getInstructionIndex(Instr);
H A DScheduleDAG.h247 MachineInstr *Instr = nullptr; ///< Alternatively, a MachineInstr. variable
320 : Instr(instr), NodeNum(nodenum), isVRegCycle(false), isCall(false),
349 assert(!Instr && "Setting SDNode of SUnit with MachineInstr!");
356 assert(!Instr && "Reading SDNode of SUnit with MachineInstr!");
362 bool isInstr() const { return Instr; }
368 Instr = MI;
375 return Instr;
/freebsd-13-stable/contrib/llvm-project/llvm/lib/MC/
H A DMCDwarf.cpp1367 void emitCFIInstruction(const MCCFIInstruction &Instr);
1376 void FrameEmitterImpl::emitCFIInstruction(const MCCFIInstruction &Instr) { argument
1380 switch (Instr.getOperation()) {
1382 unsigned Reg1 = Instr.getRegister();
1383 unsigned Reg2 = Instr.getRegister2();
1402 unsigned Reg = Instr.getRegister();
1410 Instr.getOperation() == MCCFIInstruction::OpAdjustCfaOffset;
1415 CFAOffset += Instr.getOffset();
1417 CFAOffset = Instr.getOffset();
1424 unsigned Reg = Instr
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/freebsd-13-stable/contrib/llvm-project/llvm/lib/Transforms/Vectorize/
H A DLoopVectorizationPlanner.h45 VPInstruction *Instr = new VPInstruction(Opcode, Operands); local
47 BB->insert(Instr, InsertPt);
48 return Instr;
H A DVPRecipeBuilder.h102 VPRecipeBase *tryToCreateWidenRecipe(Instruction *Instr, VFRange &Range,
H A DLoopVectorize.cpp447 /// Instr's operands.
448 void scalarizeInstruction(Instruction *Instr, VPUser &Operands,
501 void vectorizeMemoryInstruction(Instruction *Instr, VPTransformState &State,
1274 /// Check if \p Instr belongs to any interleaved access group.
1275 bool isAccessInterleaved(Instruction *Instr) { argument
1276 return InterleaveInfo.isInterleaved(Instr);
1279 /// Get the interleaved access group that \p Instr belongs to.
1281 getInterleavedAccessGroup(Instruction *Instr) { argument
1282 return InterleaveInfo.getInterleaveGroup(Instr);
1683 Instruction *Instr
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H A DVPlan.cpp52 const VPInstruction *Instr = dyn_cast<VPInstruction>(&V); local
54 (Instr && Instr->getParent()) ? Instr->getParent()->getPlan() : nullptr);
60 if (const VPInstruction *Instr = dyn_cast<VPInstruction>(this))
61 Instr->print(OS, SlotTracker);
818 O << "\"WIDEN " << VPlanIngredient(&Instr);
H A DVPlan.h1162 Instruction &Instr;
1172 return (isa<LoadInst>(Instr) && User.getNumOperands() == 2) ||
1173 (isa<StoreInst>(Instr) && User.getNumOperands() == 3);
1178 : VPRecipeBase(VPWidenMemoryInstructionSC), Instr(Load), User({Addr}) {
1184 : VPRecipeBase(VPWidenMemoryInstructionSC), Instr(Store),
1208 assert(isa<StoreInst>(Instr) &&
1877 /// Get the interleave group that \p Instr belongs to.
1881 getInterleaveGroup(VPInstruction *Instr) const {
1882 if (InterleaveGroupMap.count(Instr))
1883 return InterleaveGroupMap.find(Instr)
[all...]
/freebsd-13-stable/contrib/llvm-project/llvm/lib/CodeGen/GlobalISel/
H A DRegBankSelect.cpp848 RegBankSelect::InstrInsertPoint::InstrInsertPoint(MachineInstr &Instr, argument
850 : InsertPoint(), Instr(Instr), Before(Before) {
853 assert((!Before || !Instr.isPHI()) &&
855 assert((!Before || !Instr.getNextNode() || !Instr.getNextNode()->isPHI()) &&
884 return Instr.isTerminator();
887 return Instr.getPrevNode() && Instr.getPrevNode()->isTerminator();
897 return MBFI->getBlockFreq(Instr
[all...]
/freebsd-13-stable/contrib/llvm-project/llvm/lib/Target/Lanai/
H A DLanaiMemAluCombiner.cpp190 bool InstrUsesReg(const MbbIterator &Instr, const MachineOperand *Reg) { argument
191 for (MachineInstr::const_mop_iterator Mop = Instr->operands_begin();
192 Mop != Instr->operands_end(); ++Mop) {
H A DLanaiInstrInfo.cpp321 const MachineInstr &Instr = *I; local
323 if (Instr.modifiesRegister(Lanai::SR, TRI) ||
324 Instr.readsRegister(Lanai::SR, TRI))
356 const MachineInstr &Instr = *I; local
357 for (unsigned IO = 0, EO = Instr.getNumOperands(); !isSafe && IO != EO;
359 const MachineOperand &MO = Instr.getOperand(IO);
372 CC = (LPCC::CondCode)Instr.getOperand(IO - 1).getImm();
/freebsd-13-stable/contrib/llvm-project/llvm/lib/Target/AVR/Disassembler/
H A DAVRDisassembler.cpp41 DecodeStatus getInstruction(MCInst &Instr, uint64_t &Size,
270 DecodeStatus AVRDisassembler::getInstruction(MCInst &Instr, uint64_t &Size, argument
285 Result = decodeInstruction(getDecoderTable(Size), Instr,
298 Result = decodeInstruction(getDecoderTable(Size), Instr, Insn,
/freebsd-13-stable/contrib/llvm-project/llvm/lib/Analysis/
H A DStackLifetime.cpp341 const Instruction *Instr = dyn_cast<Instruction>(&V); variable
342 if (!Instr || !SL.isReachable(Instr))
347 if (SL.isAliveAfter(KV.getFirst(), Instr))
/freebsd-13-stable/contrib/llvm-project/clang/lib/Analysis/
H A DThreadSafetyTIL.cpp155 for (auto *Instr : Instrs)
156 Instr->setID(this, ID++);
/freebsd-13-stable/contrib/llvm-project/llvm/tools/llvm-stress/
H A Dllvm-stress.cpp712 for (auto &Instr : F->front()) {
713 if (Instr.getType() == IntegerType::getInt1Ty(F->getContext()))
714 BoolInst.push_back(&Instr);
719 for (auto *Instr : BoolInst) {
720 BasicBlock *Curr = Instr->getParent();
721 BasicBlock::iterator Loc = Instr->getIterator();
723 Instr->moveBefore(Curr->getTerminator());
725 BranchInst::Create(Curr, Next, Instr, Curr->getTerminator());
/freebsd-13-stable/contrib/llvm-project/llvm/lib/Target/PowerPC/
H A DPPCLoopInstrFormPrep.cpp1 //===------ PPCLoopInstrFormPrep.cpp - Loop Instr Form Prep Pass ----------===//
130 BucketElement(const SCEVConstant *O, Instruction *I) : Offset(O), Instr(I) {}
131 BucketElement(Instruction *I) : Offset(nullptr), Instr(I) {}
134 Instruction *Instr; member in struct:__anon4273::BucketElement
458 if (auto *II = dyn_cast<IntrinsicInst>(BucketChain.Elements[j].Instr))
502 Instruction *MemI = BucketChain.Elements.begin()->Instr;
621 Value *Ptr = GetPointerOperand(I->Instr);
637 PtrIP = I->Instr;
641 getInstrName(I->Instr, GEPNodeOffNameSuffix), PtrIP);
/freebsd-13-stable/contrib/llvm-project/llvm/lib/Target/WebAssembly/
H A DWebAssemblyRegStackify.cpp714 /// Push Instr's operands onto the stack to be visited.
715 void pushOperands(MachineInstr *Instr) { argument
716 const iterator_range<mop_iterator> &Range(Instr->explicit_uses());
721 /// Some of Instr's operands are on the top of the stack; remove them and
723 void resetTopOperands(MachineInstr *Instr) { argument
724 assert(hasRemainingOperands(Instr) &&
727 Worklist.back() = reverse(Instr->explicit_uses());
730 /// Test whether Instr has operands remaining to be visited at the top of
732 bool hasRemainingOperands(const MachineInstr *Instr) const {
736 return Range.begin() != Range.end() && Range.begin()->getParent() == Instr;
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/freebsd-13-stable/contrib/llvm-project/llvm/lib/Transforms/Scalar/
H A DGVN.cpp1829 bool GVN::replaceOperandsForInBlockEquality(Instruction *Instr) const {
1831 for (unsigned OpNum = 0; OpNum < Instr->getNumOperands(); ++OpNum) {
1832 Value *Operand = Instr->getOperand(OpNum);
1836 << *it->second << " in instruction " << *Instr << '\n');
1837 Instr->setOperand(OpNum, it->second);
2255 bool GVN::performScalarPREInsertion(Instruction *Instr, BasicBlock *Pred, argument
2262 for (unsigned i = 0, e = Instr->getNumOperands(); i != e; ++i) {
2263 Value *Op = Instr->getOperand(i);
2277 Instr->setOperand(i, V);
2290 Instr
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/freebsd-13-stable/contrib/llvm-project/llvm/lib/Target/Mips/Disassembler/
H A DMipsDisassembler.cpp73 DecodeStatus getInstruction(MCInst &Instr, uint64_t &Size,
1219 DecodeStatus MipsDisassembler::getInstruction(MCInst &Instr, uint64_t &Size, argument
1237 Result = decodeInstruction(DecoderTableMicroMipsR616, Instr, Insn,
1248 Result = decodeInstruction(DecoderTableMicroMips16, Instr, Insn, Address,
1263 Result = decodeInstruction(DecoderTableMicroMipsR632, Instr, Insn,
1273 Result = decodeInstruction(DecoderTableMicroMips32, Instr, Insn, Address,
1282 Result = decodeInstruction(DecoderTableMicroMipsFP6432, Instr, Insn,
1312 decodeInstruction(DecoderTableCOP3_32, Instr, Insn, Address, this, STI);
1320 Result = decodeInstruction(DecoderTableMips32r6_64r6_GP6432, Instr, Insn,
1329 Result = decodeInstruction(DecoderTableMips32r6_64r6_PTR6432, Instr, Ins
[all...]
/freebsd-13-stable/contrib/llvm-project/llvm/include/llvm/MC/MCDisassembler/
H A DMCDisassembler.h113 /// \param Instr - An MCInst to populate with the contents of the
126 virtual DecodeStatus getInstruction(MCInst &Instr, uint64_t &Size,
/freebsd-13-stable/contrib/llvm-project/llvm/lib/Target/Mips/
H A DMipsBranchExpansion.cpp216 Iter Instr = getNextMachineInstrInBB(Position); local
217 if (Instr == Parent->end()) {
218 return getNextMachineInstr(Instr, Parent);
220 return std::make_pair(Instr, false);
395 MachineInstrBuilder Instr = local
398 Instr.addImm(0);
/freebsd-13-stable/contrib/llvm-project/llvm/lib/IR/
H A DCore.cpp2037 if (Instruction *Instr = dyn_cast<Instruction>(unwrap(Value))) {
2038 Instr->getAllMetadata(Entries);
2723 Instruction *Instr = unwrap<Instruction>(Inst);
2724 BasicBlock::iterator I(Instr);
2725 if (++I == Instr->getParent()->end())
2731 Instruction *Instr = unwrap<Instruction>(Inst);
2732 BasicBlock::iterator I(Instr);
2733 if (I == Instr->getParent()->begin())
2781 unsigned LLVMGetNumArgOperands(LLVMValueRef Instr) {
2782 if (FuncletPadInst *FPI = dyn_cast<FuncletPadInst>(unwrap(Instr))) {
[all...]
/freebsd-13-stable/contrib/llvm-project/llvm/lib/Target/ARM/
H A DThumb2InstrInfo.cpp741 void llvm::recomputeVPTBlockMask(MachineInstr &Instr) {
742 assert(isVPTOpcode(Instr.getOpcode()) && "Not a VPST or VPT Instruction!");
744 MachineOperand &MaskOp = Instr.getOperand(0);
747 MachineBasicBlock::iterator Iter = ++Instr.getIterator(),
748 End = Instr.getParent()->end();
/freebsd-13-stable/contrib/llvm-project/llvm/lib/Target/Hexagon/Disassembler/
H A DHexagonDisassembler.cpp54 DecodeStatus getSingleInstruction(MCInst &Instr, MCInst &MCB,
57 DecodeStatus getInstruction(MCInst &Instr, uint64_t &Size,
60 void remapInstruction(MCInst &Instr) const;
199 void HexagonDisassembler::remapInstruction(MCInst &Instr) const {
200 for (auto I: HexagonMCInstrInfo::bundleInstructions(Instr)) {

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