| /freebsd-13-stable/contrib/llvm-project/llvm/lib/Target/Hexagon/ |
| H A D | HexagonISelLowering.cpp | 3262 bool HexagonTargetLowering::isFPImmLegal(const APFloat &Imm, EVT VT, argument
3316 bool HexagonTargetLowering::isLegalICmpImmediate(int64_t Imm) const {
3317 return Imm >= -512 && Imm <= 511;
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| H A D | HexagonBitSimplify.cpp | 2127 int32_t Imm = MI->getOperand(2).getImm();
2128 if (isInt<10>(Imm))
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| /freebsd-13-stable/contrib/llvm-project/llvm/lib/Target/VE/ |
| H A D | VEISelLowering.cpp | 508 bool VETargetLowering::isFPImmLegal(const APFloat &Imm, EVT VT, argument
|
| /freebsd-13-stable/contrib/llvm-project/llvm/lib/CodeGen/ |
| H A D | MachineVerifier.cpp | 1372 int64_t Imm = MI->getOperand(2).getImm(); local
1373 if (Imm <= 0)
1375 if (Imm >= SrcTy.getScalarSizeInBits())
|
| /freebsd-13-stable/contrib/llvm-project/llvm/lib/Target/ARM/ |
| H A D | ARMExpandPseudoInsts.cpp | 923 unsigned Imm = MO.getImm(); local
924 unsigned Lo16 = Imm & 0xffff;
925 unsigned Hi16 = (Imm >> 16) & 0xffff;
|
| /freebsd-13-stable/contrib/llvm-project/llvm/lib/Target/SystemZ/ |
| H A D | SystemZISelLowering.cpp | 820 bool SystemZTargetLowering::isFPImmLegal(const APFloat &Imm, EVT VT, argument
823 if (Imm.isZero() || Imm.isNegZero())
826 return SystemZVectorConstantInfo(Imm).isVectorConstantLegal(Subtarget);
838 bool SystemZTargetLowering::isLegalICmpImmediate(int64_t Imm) const {
840 return isInt<32>(Imm) || isUInt<32>(Imm);
843 bool SystemZTargetLowering::isLegalAddImmediate(int64_t Imm) const {
845 return isUInt<32>(Imm) || isUInt<32>(-Imm);
[all...] |
| /freebsd-13-stable/contrib/llvm-project/llvm/lib/Transforms/Instrumentation/ |
| H A D | MemorySanitizer.cpp | 3097 unsigned Imm = cast<ConstantInt>(I.getArgOperand(2))->getZExtValue();
3100 getPclmulMask(Width, Imm & 0x01));
3103 getPclmulMask(Width, Imm & 0x10));
|
| /freebsd-13-stable/contrib/llvm-project/llvm/lib/Target/X86/ |
| H A D | X86MCInstLower.cpp | 939 unsigned Imm = MI->getOperand(3).getImm() & 0x7; local
940 switch (Imm) {
|
| /freebsd-13-stable/contrib/llvm-project/llvm/include/llvm/CodeGen/ |
| H A D | TargetLowering.h | 993 virtual bool isFPImmLegal(const APFloat & /*Imm*/, EVT /*VT*/,
2695 virtual bool shouldConvertConstantLoadToIntImm(const APInt &Imm, argument
|
| /freebsd-13-stable/contrib/llvm-project/llvm/lib/CodeGen/SelectionDAG/ |
| H A D | TargetLowering.cpp | 3666 APInt Imm = APInt::getLowBitsSet(ExtDstTyBits, ExtSrcTyBits); local
3668 DAG.getConstant(Imm, dl, Op0Ty));
7210 APInt Imm = APInt::getLowBitsSet(IdxVT.getSizeInBits(),
7213 DAG.getConstant(Imm, dl, IdxVT));
|
| H A D | DAGCombiner.cpp | 6441 auto IsBinOpImm = [](SDValue Op, unsigned BinOpc, unsigned Imm) {
6445 return Cst && (Cst->getAPIntValue() == Imm);
15688 APInt Imm = cast<ConstantSDNode>(N1)->getAPIntValue(); local
15690 Imm ^= APInt::getAllOnesValue(BitWidth);
15691 if (Imm == 0 || Imm.isAllOnesValue())
15693 unsigned ShAmt = Imm.countTrailingZeros();
15694 unsigned MSB = BitWidth - Imm.countLeadingZeros() - 1;
15715 if ((Imm & Mask) == Imm) {
[all...] |
| H A D | SelectionDAG.cpp | 1183 APInt Imm = APInt::getLowBitsSet(OpVT.getScalarSizeInBits(),
1185 return getNode(ISD::AND, DL, OpVT, Op, getConstant(Imm, DL, OpVT));
|
| /freebsd-13-stable/contrib/llvm-project/llvm/lib/MC/MCParser/ |
| H A D | AsmParser.cpp | 5769 // It's possible to have a SizeDirective, Imm/ImmPrefix and an Input/Output
5771 // performed first, then the Imm/ImmPrefix and finally the Input/Output. This
5980 if (AR.IntelExp.Imm || AR.IntelExp.emitImm())
5981 OS << (AR.IntelExp.emitImm() ? "$$" : " + $$") << AR.IntelExp.Imm;
|
| H A D | MasmParser.cpp | 6525 // It's possible to have a SizeDirective, Imm/ImmPrefix and an Input/Output
6527 // performed first, then the Imm/ImmPrefix and finally the Input/Output. This
6801 if (AR.IntelExp.Imm || AR.IntelExp.emitImm())
6802 OS << (AR.IntelExp.emitImm() ? "$$" : " + $$") << AR.IntelExp.Imm;
|
| /freebsd-13-stable/contrib/llvm-project/llvm/lib/Target/AMDGPU/ |
| H A D | AMDGPURegisterBankInfo.cpp | 1312 if (Optional<int64_t> Imm = getConstantVRegVal(CombinedOffset, *MRI)) {
1314 if (AMDGPU::splitMUBUFOffset(*Imm, SOffset, ImmOffset, &RBI.Subtarget,
|
| H A D | SIISelLowering.cpp | 1488 bool SITargetLowering::shouldConvertConstantLoadToIntImm(const APInt &Imm, argument
7643 uint32_t Imm = C->getZExtValue(); local
7645 if (AMDGPU::splitMUBUFOffset(Imm, SOffset, ImmOffset, Subtarget,
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| H A D | AMDGPUISelLowering.cpp | 699 bool AMDGPUTargetLowering::isFPImmLegal(const APFloat &Imm, EVT VT, argument
|
| /freebsd-13-stable/contrib/llvm-project/clang/lib/Sema/ |
| H A D | SemaChecking.cpp | 2090 llvm::APSInt Imm;
2091 if (SemaBuiltinConstantArg(TheCall, ArgNum, Imm))
2094 if (!CheckImm(Imm.getSExtValue()))
|
| /freebsd-13-stable/contrib/llvm-project/llvm/lib/CodeGen/GlobalISel/ |
| H A D | LegalizerHelper.cpp | 3383 int64_t Imm = MI.getOperand(2).getImm(); local
3392 R = MIRBuilder.buildSExtInReg(NarrowTy, R, Imm).getReg(0);
|