Searched refs:phy (Results 101 - 125 of 265) sorted by relevance

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/freebsd-12-stable/sys/dev/e1000/
H A De1000_mac.c1009 /* In the case of the phy reset being blocked, we already have a link.
1012 if (hw->phy.ops.check_reset_block && hw->phy.ops.check_reset_block(hw))
1211 if (hw->phy.media_type == e1000_media_type_internal_serdes ||
1367 if (hw->phy.media_type == e1000_media_type_fiber ||
1368 hw->phy.media_type == e1000_media_type_internal_serdes)
1371 if (hw->phy.media_type == e1000_media_type_copper)
1385 if ((hw->phy.media_type == e1000_media_type_copper) && mac->autoneg) {
1390 ret_val = hw->phy.ops.read_reg(hw, PHY_STATUS, &mii_status_reg);
1393 ret_val = hw->phy
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H A De1000_vf.c65 hw->phy.type = e1000_phy_vf;
66 hw->phy.ops.acquire = e1000_acquire_vf;
67 hw->phy.ops.release = e1000_release_vf;
104 hw->phy.media_type = e1000_media_type_unknown;
151 hw->phy.ops.init_params = e1000_init_phy_params_vf;
H A De1000_i210.c589 switch (hw->phy.media_type) {
618 ret_val = hw->phy.ops.write_reg(hw, E1000_MMDAC, dev_addr);
622 ret_val = hw->phy.ops.write_reg(hw, E1000_MMDAAD, address);
626 ret_val = hw->phy.ops.write_reg(hw, E1000_MMDAC, E1000_MMDAC_FUNC_DATA |
632 ret_val = hw->phy.ops.read_reg(hw, E1000_MMDAAD, data);
634 ret_val = hw->phy.ops.write_reg(hw, E1000_MMDAAD, *data);
639 ret_val = hw->phy.ops.write_reg(hw, E1000_MMDAC, 0);
787 hw->phy.ops.get_cfg_done = e1000_get_cfg_done_i210;
H A De1000_82542.c61 struct e1000_phy_info *phy = &hw->phy; local
66 phy->type = e1000_phy_none;
108 hw->phy.media_type = e1000_media_type_fiber;
127 /* phy/fiber/serdes setup */
166 hw->phy.ops.init_params = e1000_init_phy_params_82542;
/freebsd-12-stable/sys/dev/isci/scil/
H A Dscic_sds_controller.h220 * This field is the array of phy objects that are controlled by this
357 * This field is the driver timer handle for controller phy request startup.
359 * order of phy index.
370 * This field is the index of the next phy start. It is initialized to 0 and
371 * increments for each phy index that is started.
430 struct SCIC_SDS_PHY *phy
587 * This macro will set the bit in the invalid phy mask for this controller
591 #define scic_sds_controller_set_invalid_phy(controller, phy) \
592 ((controller)->invalid_phy_mask |= (1 << (phy)->phy_index))
595 * This macro will clear the bit in the invalid phy mas
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H A Dscif_sas_domain.c403 SCI_PHY_HANDLE_T phy
416 controller, port, phy
441 SCI_PHY_HANDLE_T phy
448 controller, port, phy
457 SCI_PHY_HANDLE_T phy
464 controller, port, phy
473 SCI_PHY_HANDLE_T phy
480 controller, port, phy
489 SCI_PHY_HANDLE_T phy
499 controller, port, phy
[all...]
/freebsd-12-stable/sys/arm/nvidia/
H A Dtegra_ehci.c49 #include <dev/extres/phy/phy.h>
80 phy_t phy; member in struct:tegra_ehci_softc
184 rv = phy_get_by_ofw_property(sc->dev, 0, "nvidia,phy", &sc->phy);
186 device_printf(sc->dev, "Cannot get 'nvidia,phy' phy\n");
217 rv = phy_enable(sc->phy);
219 device_printf(dev, "Cannot enable phy: %d\n", rv);
/freebsd-12-stable/sys/dev/bwn/
H A Dif_bwn.c1376 KASSERT(0 == 1, ("%s: unknown phy type (%d)", __func__,
1566 struct bwn_phy *phy = &mac->mac_phy; local
1572 phy->gmode = gmode;
1573 phy->rf_on = 1;
1574 phy->analog = (tmp & BWN_PHYVER_ANALOG) >> 12;
1575 phy->type = (tmp & BWN_PHYVER_TYPE) >> 8;
1576 phy->rev = (tmp & BWN_PHYVER_VERSION);
1577 if ((phy->type == BWN_PHYTYPE_A && phy->rev >= 4) ||
1578 (phy
1965 struct bwn_phy *phy = &mac->mac_phy; local
2401 struct bwn_phy *phy = &mac->mac_phy; local
3843 struct bwn_phy *phy = &mac->mac_phy; local
4555 struct bwn_phy *phy = &(mac->mac_phy); local
5929 struct bwn_phy *phy = &mac->mac_phy; local
6230 struct bwn_phy *phy = &mac->mac_phy; local
6326 struct bwn_phy *phy = &mac->mac_phy; local
6398 const struct bwn_phy *phy = &mac->mac_phy; local
[all...]
/freebsd-12-stable/sys/cam/scsi/
H A Dsmp_all.c525 int ignore_zone_group, int phy, uint32_t timeout)
544 request->phy = phy;
585 uint32_t expected_exp_change_count, int phy, int phy_op,
607 request->phy = phy;
521 smp_discover(struct ccb_smpio *smpio, uint32_t retries, void (*cbfcnp)(struct cam_periph *, union ccb *), struct smp_discover_request *request, int request_len, uint8_t *response, int response_len, int long_response, int ignore_zone_group, int phy, uint32_t timeout) argument
581 smp_phy_control(struct ccb_smpio *smpio, uint32_t retries, void (*cbfcnp)(struct cam_periph *, union ccb *), struct smp_phy_control_request *request, int request_len, uint8_t *response, int response_len, int long_response, uint32_t expected_exp_change_count, int phy, int phy_op, int update_pp_timeout_val, uint64_t attached_device_name, int prog_min_prl, int prog_max_prl, int slumber_partial, int pp_timeout_value, uint32_t timeout) argument
H A Dsmp_all.h254 uint8_t phy; member in struct:smp_discover_request
268 uint8_t phy; member in struct:smp_discover_response
410 uint8_t phy; member in struct:smp_phy_control_request
504 int ignore_zone_group, int phy, uint32_t timeout);
516 uint32_t expected_exp_change_count, int phy, int phy_op,
/freebsd-12-stable/sys/dev/etherswitch/
H A Detherswitch.c188 phyreg->val = ETHERSWITCH_READPHYREG(etherswitch, phyreg->phy, phyreg->reg);
193 error = ETHERSWITCH_WRITEPHYREG(etherswitch, phyreg->phy, phyreg->reg, phyreg->val);
H A Dmiiproxy.c283 miiproxy_readreg(device_t dev, int phy, int reg) argument
288 return (MDIO_READREG(sc->mdio, phy, reg));
293 miiproxy_writereg(device_t dev, int phy, int reg, int val) argument
298 return (MDIO_WRITEREG(sc->mdio, phy, reg, val));
/freebsd-12-stable/sys/dev/etherswitch/rtl8366/
H A Drtl8366rbvar.h177 #define RTL8366_PHYREG(phy, page, reg) \
178 (0x8000 | (1 << (((phy) & 0x1f) + 9)) | (((page) & (sc->chip_type == 0 ? 0xf : 0x7)) << 5) | ((reg) & 0x1f))
H A Drtl8366rb.c829 rtl_readphy(device_t dev, int phy, int reg) argument
839 if (phy < 0 || phy >= RTL8366_NUM_PHYS)
850 err = smi_write_locked(sc, RTL8366_PHYREG(phy, 0, reg), 0, sleep);
860 DEVERR(dev, err, "rtl_readphy()=%d: phy=%d.%02x\n", phy, reg);
865 rtl_writephy(device_t dev, int phy, int reg, int data) argument
872 if (phy < 0 || phy >= RTL8366_NUM_PHYS)
883 err = smi_write_locked(sc, RTL8366_PHYREG(phy,
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/freebsd-12-stable/sys/dev/rtwn/rtl8192c/
H A Dr92c_rx.c84 struct r92c_rx_phystat *phy = (struct r92c_rx_phystat *)physt; local
88 rssi = ((phy->pwdb_all >> 1) & 0x7f) - 110;
/freebsd-12-stable/sys/dev/ath/ath_rate/sample/
H A Dsample.h158 * XXX getting mac/phy level timings should be fixed for turbo
162 switch (rt->info[rix].phy) {
190 rt->info[rix].phy == IEEE80211_T_OFDM) {
/freebsd-12-stable/sys/net80211/
H A Dieee80211_phy.h90 uint8_t phy; /* CCK/OFDM/TURBO */ member in struct:ieee80211_rate_table::__anon15972
148 return rt->info[rix].phy;
168 * sent using rate, phy and short preamble setting.
198 * using the specified 802.11 rate code, phy, and short preamble
/freebsd-12-stable/sys/dev/etherswitch/ip17x/
H A Dip175c.c86 int i, err, phy; local
94 phy = sc->portphy[i];
96 ports[phy] = v->ports;
/freebsd-12-stable/sys/dev/bwi/
H A Dbwimac.c596 struct bwi_phy *phy = &mac->mac_phy; local
622 if (phy->phy_mode == IEEE80211_MODE_11A) {
648 if (phy->phy_mode == IEEE80211_MODE_11G) {
661 if (phy->phy_mode == IEEE80211_MODE_11G) {
761 struct bwi_phy *phy = &mac->mac_phy; local
766 KASSERT(phy->phy_mode != IEEE80211_MODE_11A,
767 ("phy_mode %d", phy->phy_mode));
775 if (phy->phy_mode == IEEE80211_MODE_11G) {
776 if ((phy->phy_flags & BWI_PHY_F_LINKED) == 0)
783 if (phy
1310 struct bwi_phy *phy = &mac->mac_phy; local
1339 struct bwi_phy *phy = &mac->mac_phy; local
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/freebsd-12-stable/sys/dev/etherswitch/arswitch/
H A Darswitch_8327.c155 ar8327_phy_fixup(struct arswitch_softc *sc, int phy) argument
159 "%s: called; phy=%d; chiprev=%d\n", __func__,
160 phy,
165 arswitch_writedbg(sc->sc_dev, phy, 0, 0x02ea);
167 arswitch_writedbg(sc->sc_dev, phy, 0x3d, 0x68a0);
171 arswitch_writemmd(sc->sc_dev, phy, 0x7, 0x3c);
172 arswitch_writemmd(sc->sc_dev, phy, 0x4007, 0x0);
175 arswitch_writemmd(sc->sc_dev, phy, 0x3, 0x800d);
176 arswitch_writemmd(sc->sc_dev, phy, 0x4003, 0x803f);
178 arswitch_writedbg(sc->sc_dev, phy,
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/freebsd-12-stable/sbin/etherswitchcfg/
H A Detherswitchcfg.c147 read_phyregister(struct cfg *cfg, int phy, int reg) argument
151 er.phy = phy;
159 write_phyregister(struct cfg *cfg, int phy, int reg, int val) argument
163 er.phy = phy;
415 int phy, reg, val; local
418 phy = strtol(arg, &c, 0);
429 write_phyregister(cfg, phy, reg, val);
431 printf("\treg %d.0x%02x=0x%04x\n", phy, re
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/freebsd-12-stable/sys/dev/pms/RefTisa/sallsdk/spc/
H A Dsainit.c864 /* setup phy status is PHY_STOPPED */
2515 /* setup phy analog registers */
3146 /* read phy attribute table offset */
3950 /* setup phy status is PHY_STOPPED */
4199 bit32 AnalogTableBase,CFGTableOffset, value,phy; local
4218 for(phy = 0; phy < 10; phy++) /* upto 10 phys See PM*/
4220 ossaHwRegWriteExt(agRoot, pcibar,(AnalogTableBase + ( AnalogtableSize * phy)+ 0 ),config->phyAnalogConfig.phyAnalogSetupRegisters[phy]
[all...]
/freebsd-12-stable/sys/gnu/dev/bwn/phy_n/
H A Dif_bwn_radio_2057.c592 struct bwn_phy *phy = &mac->mac_phy; local
596 switch (phy->rev) {
602 if (phy->rf_rev == 5) {
605 } else if (phy->rf_rev == 7) {
611 if (phy->rf_rev == 5) {
617 if (phy->rf_rev == 9) {
623 if (phy->rf_rev == 14) {
632 "%s: couldn't find a suitable table (phy ref=%d, rf_ref=%d)\n",
634 phy->rev,
635 phy
648 struct bwn_phy *phy = &mac->mac_phy; local
[all...]
/freebsd-12-stable/sys/dev/mge/
H A Dif_mge.c97 static int mge_miibus_readreg(device_t dev, int phy, int reg);
98 static int mge_miibus_writereg(device_t dev, int phy, int reg, int value);
100 static int mge_mdio_readreg(device_t dev, int phy, int reg);
101 static int mge_mdio_writereg(device_t dev, int phy, int reg, int value);
211 mv_read_ge_smi(device_t dev, int phy, int reg) argument
233 (MGE_SMI_READ | (reg << 21) | (phy << 16)));
258 mv_write_ge_smi(device_t dev, int phy, int reg, uint32_t value) argument
278 (MGE_SMI_WRITE | (reg << 21) | (phy << 16) |
286 mv_read_ext_phy(device_t dev, int phy, int reg) argument
296 (MGE_SMI_READ | (reg << 21) | (phy << 1
313 mv_write_ext_phy(device_t dev, int phy, int reg, int value) argument
789 int i, error, phy; local
1583 mge_miibus_readreg(device_t dev, int phy, int reg) argument
1594 mge_miibus_writereg(device_t dev, int phy, int reg, int value) argument
2152 mge_mdio_writereg(device_t dev, int phy, int reg, int value) argument
2162 mge_mdio_readreg(device_t dev, int phy, int reg) argument
[all...]
/freebsd-12-stable/sys/dev/cxgb/
H A Dcxgb_main.c974 desc = p->phy.desc;
1251 * @phy: the PHY reporting the module change
1264 int mod = pi->phy.modtype;
1729 t3_link_start(&p->phy, mac, &p->link_config);
1746 p->phy.caps & SUPPORTED_LINK_IRQ ? hz * 3 : hz / 4,
1846 pi->phy.ops->power_down(&pi->phy, 1);
2070 * Translates phy->modtype to the correct Ethernet media subtype.
2102 struct cphy *phy = &p->phy; local
2559 struct cphy *phy = &pi->phy; local
2581 struct cphy *phy = &pi->phy; local
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