| /freebsd-12-stable/contrib/llvm-project/clang/include/clang/Analysis/Analyses/ |
| H A D | ThreadSafetyTIL.h | 310 /// All basic block instructions have a unique ID (i.e. virtual register).
1497 /// instructions. It ends with a Terminator, which is a Branch or Goto to
1555 InstrArray &instructions() { return Instrs; } function in class:clang::threadSafety::BasicBlock
1556 const InstrArray &instructions() const { return Instrs; } function in class:clang::threadSafety::BasicBlock
1599 // Reserve space for Nins instructions.
1644 // assign unique ids to all instructions
1736 /// Return the total number of instructions in the CFG.
1772 // assign unique ids to all instructions
1854 /// This is a pseduo-term; it will be lowered to instructions in a CFG.
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| /freebsd-12-stable/crypto/openssl/crypto/poly1305/asm/ |
| H A D | poly1305-armv4.pl | 573 @ to minimize amount of instructions [as well as amount of
574 @ 128-bit instructions, which benefits low-end processors], but
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| /freebsd-12-stable/contrib/llvm-project/clang/lib/Analysis/ |
| H A D | ThreadSafetyCommon.cpp | 898 CurrentBB->instructions().reserve(
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| /freebsd-12-stable/lib/libpmc/ |
| H A D | libpmc.c | 90 * like "cache-misses", or "instructions-retired". These aliases are
376 EV_ALIAS("instructions", "k8-fr-retired-x86-instructions"),
413 __K8MASK(locked-instructions, 0),
436 /* dc dispatched prefetch instructions */
476 /* fr retired fpu instructions */
485 /* fr retired fastpath double op instructions */
741 EV_ALIAS("instructions", "SOFT-CLOCK.HARD"),
767 EV_ALIAS("instructions", "INSTR_RETIRED"),
786 EV_ALIAS("instructions", "INSTR_EXECUTE
[all...] |
| /freebsd-12-stable/contrib/llvm-project/llvm/lib/IR/ |
| H A D | Function.cpp | 290 dropAllReferences(); // After this it is safe to delete instructions.
1476 for (const Instruction &I : instructions(this))
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| /freebsd-12-stable/contrib/llvm-project/llvm/lib/Transforms/Coroutines/ |
| H A D | CoroSplit.cpp | 955 // Add musttail to any resume instructions that is immediately followed by a
963 // Collect potential resume instructions.
965 for (auto &I : instructions(F))
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| /freebsd-12-stable/contrib/llvm-project/llvm/lib/Transforms/Instrumentation/ |
| H A D | GCOVProfiling.cpp | 638 for (auto &I : instructions(F)) {
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| /freebsd-12-stable/secure/lib/libcrypto/arm/ |
| H A D | bsaes-armv7.S | 1876 @ put this in range for both ARM and Thumb mode adr instructions
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| /freebsd-12-stable/crypto/openssl/ |
| H A D | Configure | 22 # see INSTALL for instructions.
673 # some people just can't read the instructions, clang people have to...
1077 INSTALL instructions and the RAND_DRBG(7) manual page for more details.
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| /freebsd-12-stable/crypto/openssl/crypto/bn/asm/ |
| H A D | armv8-mont.pl | 29 # umulh and therefore uses same amount of multiplication instructions
31 # instructions and of course instruction scheduling.
106 // instructions. The outcome of first addition is
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| /freebsd-12-stable/contrib/llvm-project/llvm/lib/Bitcode/Reader/ |
| H A D | BitcodeReader.cpp | 166 for (auto &I : instructions(F))
5288 for (auto &I : instructions(F)) {
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| /freebsd-12-stable/contrib/llvm-project/llvm/lib/CodeGen/SelectionDAG/ |
| H A D | SelectionDAGISel.cpp | 114 STATISTIC(NumFastIselFailures, "Number of instructions fast isel failed on");
115 STATISTIC(NumFastIselSuccess, "Number of instructions fast isel selected");
280 // that mark instructions with the 'usesCustomInserter' flag. These
281 // instructions are special in various ways, which require special support to
284 // instructions, potentially also creating new basic blocks and control flow.
395 for (const Instruction &I : instructions(F)) {
571 // Insert DBG_VALUE instructions for function arguments to the entry block.
611 // that COPY instructions also need DBG_VALUE, if it is the only
722 // Lower the instructions. If a call is emitted as a tail call, cease emitting
999 // scheduled instructions
[all...] |
| /freebsd-12-stable/crypto/openssl/crypto/aes/asm/ |
| H A D | bsaes-armv7.pl | 1866 @ put this in range for both ARM and Thumb mode adr instructions
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| /freebsd-12-stable/contrib/binutils/gas/config/ |
| H A D | tc-mips.c | 85 /* Control generation of error message for unsupported instructions in
86 Octeon. Octeon does not have floating point, and all the instructions
95 /* Control generation of Octeon/MIPS unaligned load/store instructions.
96 For ELF target, default to Octeon load/store instructions.
97 For Linux target, default to MIPS load/store instructions. */
173 /* True for mips16 instructions that jump to an absolute address. */
222 /* Non-zero if we should not reorder instructions. Changed by `.set
226 in instructions. Changed by `.set at' and `.set noat'. */
232 /* Non-zero if we should not move instructions. Changed by `.set
240 /* Non-zero if we should not autoextend mips16 instructions
[all...] |
| /freebsd-12-stable/crypto/openssl/crypto/ec/asm/ |
| H A D | ecp_nistz256-sparcv9.pl | 1899 ! instructions, but only 14% faster [on T4]...
3022 # Purpose of these subroutines is to explicitly encode VIS instructions,
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| /freebsd-12-stable/contrib/llvm-project/llvm/lib/Transforms/IPO/ |
| H A D | Attributor.cpp | 259 /// will be done by looking through cast instructions, selects, phis, and calls
316 // Look through select instructions, visit both potential values.
326 "Expected liveness in the presence of instructions!");
935 /// instructions that they arise from.
942 /// return instructions that might return them.
975 // The map from instruction opcodes to those instructions in the function.
1220 // Start by discovering returned values from all live returned instructions in
1480 /// We are looking for volatile instructions or Non-Relaxed atomics.
2030 // Skip instructions that are already saved.
2051 // Because we only consider instructions insid
[all...] |
| /freebsd-12-stable/contrib/llvm-project/llvm/lib/Analysis/ |
| H A D | ScalarEvolution.cpp | 621 // For instructions, compare their loop depth, and their operand count. This
4678 // vectorizer induction analysis), a Set of cast instructions will be
5438 /// Expand GEP instructions into add and multiply operations. This allows them
6025 // since we only deal with instructions in the loop header. The actual loop we
6041 // instructions can map to the same SCEV. If we apply NSW or NUW from I to
6043 // derived from other instructions that map to the same SCEV. We cannot make
6180 // Don't attempt to analyze instructions in blocks that aren't
6181 // reachable. Such instructions don't matter, and they aren't required
6532 // constant expressions cannot have instructions as operands, we'd have
7854 // Record non-constant instructions containe
[all...] |