/freebsd-12-stable/contrib/llvm-project/llvm/lib/Target/X86/ |
H A D | X86WinAllocaExpander.cpp | 221 .addReg(RegA, RegState::Undef); 235 .addReg(RegA, RegState::Undef);
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H A D | X86FixupBWInsts.cpp | 335 .addReg(NewSrcReg, RegState::Undef) 336 .addReg(OldSrc.getReg(), RegState::Implicit);
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H A D | X86FixupLEAs.cpp | 397 .addReg(Base.getReg(), RegState::Implicit) 398 .addReg(Index.getReg(), RegState::Implicit); 417 .addReg(BaseReg).addReg(Base.getReg(), RegState::Implicit); 428 .addReg(Base.getReg(), RegState::Implicit); 586 .addReg(Base.getReg(), RegState::Implicit) 587 .addReg(Index.getReg(), RegState::Implicit);
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H A D | X86CallLowering.cpp | 126 MIB.addUse(PhysReg, RegState::Implicit); 318 MIB.addDef(PhysReg, RegState::Implicit); 441 MIB.addUse(X86::AL, RegState::Implicit);
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/freebsd-12-stable/contrib/llvm-project/llvm/lib/Target/AMDGPU/ |
H A D | SIInsertSkips.cpp | 170 .addReg(AMDGPU::VGPR0, RegState::Undef) 171 .addReg(AMDGPU::VGPR0, RegState::Undef) 172 .addReg(AMDGPU::VGPR0, RegState::Undef) 173 .addReg(AMDGPU::VGPR0, RegState::Undef) 262 I.addReg(AMDGPU::VCC, RegState::Define);
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H A D | SIAddIMGInit.cpp | 168 MachineInstrBuilder(MF, MI).addReg(NewDst, RegState::Implicit);
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H A D | SIInstrInfo.cpp | 679 .addReg(Tmp, RegState::Kill); 733 Builder.addReg(DestReg, RegState::Define | RegState::Implicit); 736 Builder.addReg(SrcReg, getKillRegState(UseKill) | RegState::Implicit); 1089 .addReg(MFI->getScratchRSrcReg(), RegState::Implicit) 1090 .addReg(MFI->getStackPtrOffsetReg(), RegState::Implicit); 1107 MIB.addReg(Tmp, RegState::Define); 1216 .addReg(MFI->getScratchRSrcReg(), RegState::Implicit) 1217 .addReg(MFI->getStackPtrOffsetReg(), RegState::Implicit); 1227 MIB.addReg(Tmp, RegState [all...] |
H A D | R600InstrInfo.cpp | 85 RegState::Define | RegState::Implicit); 777 .addReg(R600::PREDICATE_BIT, RegState::Kill); 792 .addReg(R600::PREDICATE_BIT, RegState::Kill); 990 MIB.addReg(R600::PREDICATE_BIT, RegState::Implicit); 998 MIB.addReg(R600::PREDICATE_BIT, RegState::Implicit); 1140 RegState::Implicit | RegState::Kill); 1173 RegState::Implicit | RegState [all...] |
H A D | SILoadStoreOptimizer.cpp | 997 BaseRegFlags = RegState::Kill; 1024 .addReg(DestReg, RegState::Kill, SubRegIdx1); 1090 BaseRegFlags = RegState::Kill; 1162 .addReg(DestReg, RegState::Kill, SubRegIdx1); 1212 .addReg(DestReg, RegState::Kill, SubRegIdx1); 1274 .addReg(DestReg, RegState::Kill, SubRegIdx1); 1341 .addReg(DestReg, RegState::Kill, SubRegIdx1); 1375 .addReg(SrcReg, RegState::Kill); 1537 .addReg(SrcReg, RegState::Kill); 1615 .addReg(CarryReg, RegState [all...] |
/freebsd-12-stable/contrib/llvm-project/llvm/lib/Target/Mips/ |
H A D | MipsExpandPseudo.cpp | 158 .addReg(Scratch, RegState::Kill) 161 .addReg(Scratch, RegState::Kill) 164 .addReg(Scratch, RegState::Kill) 168 .addReg(Scratch, RegState::Kill) 184 .addReg(Dest, RegState::Kill) 187 .addReg(Dest, RegState::Kill) 280 .addReg(Dest, RegState::Kill).addReg(OldVal).addMBB(exitMBB); 290 .addReg(Scratch, RegState::Kill).addReg(ZERO).addMBB(loop1MBB); 559 .addReg(Dest, RegState::Kill) 562 .addReg(Dest, RegState [all...] |
H A D | MipsSEInstrInfo.cpp | 112 .addReg(SrcReg, RegState::Implicit | getKillRegState(KillSrc)); 134 .addReg(DestReg, RegState::ImplicitDefine); 177 MIB.addReg(DestReg, RegState::Define); 597 BuildMI(MBB, I, DL, get(Opc), SP).addReg(SP).addReg(Reg, RegState::Kill); 636 BuildMI(MBB, II, DL, get(Inst->Opc), Reg).addReg(Reg, RegState::Kill) 678 .addReg(Mips::RA_64, RegState::Undef); 681 .addReg(Mips::RA, RegState::Undef); 735 LoInst.addReg(DstLo, RegState::Define); 736 HiInst.addReg(DstHi, RegState::Define); 764 BuildMI(MBB, I, DL, CvtDesc, DstReg).addReg(TmpReg, RegState [all...] |
H A D | MipsISelLowering.cpp | 1599 .addReg(OldVal, RegState::Define | RegState::EarlyClobber) 1602 .addReg(Scratch, RegState::Define | RegState::EarlyClobber | 1603 RegState::Implicit | RegState::Dead); 1607 MIB.addReg(Scratch2, RegState::Define | RegState::EarlyClobber | 1608 RegState::Implicit | RegState [all...] |
H A D | MipsSEISelDAGToDAG.cpp | 57 IsDef ? RegState::ImplicitDefine : RegState::Implicit | RegState::Undef; 135 .addUse(Mips::RA_64, RegState::Undef) 138 MIB.addUse(Mips::AT_64, RegState::Implicit); 143 .addUse(Mips::RA, RegState::Undef) 151 MIB.addUse(Mips::AT, RegState::Implicit);
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/freebsd-12-stable/contrib/llvm-project/llvm/lib/Target/ARM/ |
H A D | Thumb2InstrInfo.cpp | 209 AddDReg(MIB, DestReg, ARM::gsub_0, RegState::DefineNoRead, TRI); 210 AddDReg(MIB, DestReg, ARM::gsub_1, RegState::DefineNoRead, TRI); 214 MIB.addReg(DestReg, RegState::ImplicitDefine); 239 .addReg(BaseReg, RegState::Kill) 272 .addReg(DestReg, RegState::Kill) 284 .addReg(DestReg, RegState::Kill) 349 .addReg(BaseReg, RegState::Kill)
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H A D | ARMInstrInfo.cpp | 132 .addReg(Reg, RegState::Kill)
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H A D | ThumbRegisterInfo.cpp | 160 .addReg(LdReg, RegState::Kill) 176 MIB.addReg(BaseReg).addReg(LdReg, RegState::Kill); 178 MIB.addReg(LdReg).addReg(BaseReg, RegState::Kill); 315 MIB.addReg(BaseReg, RegState::Kill);
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H A D | ARMLoadStoreOptimizer.cpp | 844 MIB.addReg(Regs[0].first, RegState::Define) 845 .addReg(Regs[1].first, RegState::Define); 956 MIB.addReg(ImpDef, RegState::ImplicitDefine); 1460 .addReg(Base, RegState::Define) 1466 .addReg(Base, RegState::Define) 1476 .addReg(Base, RegState::Define) 1550 MIB.add(Reg0Op).add(Reg1Op).addReg(BaseOp.getReg(), RegState::Define); 1553 MIB.addReg(BaseOp.getReg(), RegState::Define).add(Reg0Op).add(Reg1Op); 1555 MIB.addReg(BaseOp.getReg(), RegState::Kill) 1992 .addReg(Use.getReg(), RegState [all...] |
/freebsd-12-stable/contrib/llvm-project/llvm/lib/Target/RISCV/ |
H A D | RISCVRegisterInfo.cpp | 139 .addReg(ScratchReg, RegState::Kill);
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/freebsd-12-stable/contrib/llvm-project/llvm/lib/Target/SystemZ/ |
H A D | SystemZElimCompare.cpp | 236 MIB.addReg(SystemZ::CC, RegState::ImplicitDefine | RegState::Dead); 678 RegState::ImplicitDefine | RegState::Dead);
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H A D | SystemZShortenInst.cpp | 146 .addReg(SystemZ::CC, RegState::ImplicitDefine | RegState::Dead);
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H A D | SystemZFrameLowering.cpp | 338 MIB.addReg(RestoreGPRs.LowGPR, RegState::Define); 339 MIB.addReg(RestoreGPRs.HighGPR, RegState::Define); 350 MIB.addReg(Reg, RegState::ImplicitDefine); 503 .addReg(SystemZ::R1D, RegState::Define).addReg(SystemZ::R15D); 518 .addReg(SystemZ::R1D, RegState::Kill).addReg(SystemZ::R15D).addImm(0)
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/freebsd-12-stable/contrib/llvm-project/llvm/lib/Target/MSP430/ |
H A D | MSP430FrameLowering.cpp | 67 .addReg(MSP430::FP, RegState::Kill); 200 .addReg(Reg, RegState::Kill);
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/freebsd-12-stable/contrib/llvm-project/llvm/lib/CodeGen/MIRParser/ |
H A D | MIParser.cpp | 1335 Flags |= RegState::Implicit; 1338 Flags |= RegState::ImplicitDefine; 1341 Flags |= RegState::Define; 1344 Flags |= RegState::Dead; 1347 Flags |= RegState::Kill; 1350 Flags |= RegState::Undef; 1353 Flags |= RegState::InternalRead; 1356 Flags |= RegState::EarlyClobber; 1359 Flags |= RegState::Debug; 1362 Flags |= RegState [all...] |
/freebsd-12-stable/contrib/llvm-project/llvm/lib/Target/AArch64/ |
H A D | AArch64CallLowering.cpp | 124 MIB.addDef(PhysReg, RegState::Implicit); 171 MIB.addUse(PhysReg, RegState::Implicit); 365 MIB.addUse(AArch64::X21, RegState::Implicit); 889 MIB.addReg(ForwardedReg, RegState::Implicit); 1013 MIB.addDef(AArch64::X21, RegState::Implicit);
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H A D | AArch64InstrInfo.cpp | 1492 .addReg(AArch64::X0, RegState::Define) 1495 .addReg(AArch64::X0, RegState::Define) 1515 .addDef(Reg32, RegState::Dead) 1516 .addUse(Reg, RegState::Kill) 1519 .addDef(Reg, RegState::Implicit); 1522 .addReg(Reg, RegState::Kill) 1532 .addReg(Reg, RegState::Kill) 1536 .addReg(Reg, RegState::Kill) 1540 .addReg(Reg, RegState::Kill) 1544 .addReg(Reg, RegState [all...] |