/freebsd-12-stable/contrib/llvm-project/llvm/lib/Target/ARM/ |
H A D | ARMISelLowering.h | 795 const SmallVectorImpl<SDValue> &OutVals, 806 const SmallVectorImpl<SDValue> &OutVals,
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H A D | ARMISelLowering.cpp | 2090 SmallVectorImpl<SDValue> &OutVals = CLI.OutVals; local 2127 MF.getFunction().hasStructRetAttr(), Outs, OutVals, Ins, DAG, 2168 SDValue Arg = OutVals[realArgIdx]; 2483 isThisReturn ? OutVals[0] : SDValue()); 2591 const SmallVectorImpl<SDValue> &OutVals, 2677 SDValue Arg = OutVals[realArgIdx]; 2705 if (!parametersInCSRMatch(MRI, CallerPreserved, ArgLocs, OutVals)) 2759 const SmallVectorImpl<SDValue> &OutVals, 2787 SDValue Arg = OutVals[realRVLocId 2587 IsEligibleForTailCallOptimization( SDValue Callee, CallingConv::ID CalleeCC, bool isVarArg, bool isCalleeStructRet, bool isCallerStructRet, const SmallVectorImpl<ISD::OutputArg> &Outs, const SmallVectorImpl<SDValue> &OutVals, const SmallVectorImpl<ISD::InputArg> &Ins, SelectionDAG &DAG, const bool isIndirect) const argument 2756 LowerReturn(SDValue Chain, CallingConv::ID CallConv, bool isVarArg, const SmallVectorImpl<ISD::OutputArg> &Outs, const SmallVectorImpl<SDValue> &OutVals, const SDLoc &dl, SelectionDAG &DAG) const argument [all...] |
/freebsd-12-stable/contrib/llvm-project/llvm/lib/Target/RISCV/ |
H A D | RISCVISelLowering.cpp | 2134 SmallVectorImpl<SDValue> &OutVals = CLI.OutVals; local 2175 SDValue Arg = OutVals[i]; 2200 SDValue ArgValue = OutVals[i]; 2249 SDValue PartValue = OutVals[i + 1]; 2423 const SmallVectorImpl<SDValue> &OutVals, 2443 SDValue Val = OutVals[i]; 2420 LowerReturn(SDValue Chain, CallingConv::ID CallConv, bool IsVarArg, const SmallVectorImpl<ISD::OutputArg> &Outs, const SmallVectorImpl<SDValue> &OutVals, const SDLoc &DL, SelectionDAG &DAG) const argument
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/freebsd-12-stable/contrib/llvm-project/llvm/lib/Target/Hexagon/ |
H A D | HexagonISelLowering.cpp | 196 const SmallVectorImpl<SDValue> &OutVals, 218 Chain = DAG.getCopyToReg(Chain, dl, VA.getLocReg(), OutVals[i], Flag); 322 const SmallVectorImpl<SDValue> &OutVals, SDValue Callee) const { 377 SmallVectorImpl<SDValue> &OutVals = CLI.OutVals; local 410 OutVals, Ins, DAG); 436 SDValue Arg = OutVals[i]; 593 InVals, OutVals, Callee); 3180 const SmallVectorImpl<SDValue> &OutVals, 193 LowerReturn(SDValue Chain, CallingConv::ID CallConv, bool IsVarArg, const SmallVectorImpl<ISD::OutputArg> &Outs, const SmallVectorImpl<SDValue> &OutVals, const SDLoc &dl, SelectionDAG &DAG) const argument 318 LowerCallResult( SDValue Chain, SDValue Glue, CallingConv::ID CallConv, bool IsVarArg, const SmallVectorImpl<ISD::InputArg> &Ins, const SDLoc &dl, SelectionDAG &DAG, SmallVectorImpl<SDValue> &InVals, const SmallVectorImpl<SDValue> &OutVals, SDValue Callee) const argument 3173 IsEligibleForTailCallOptimization( SDValue Callee, CallingConv::ID CalleeCC, bool IsVarArg, bool IsCalleeStructRet, bool IsCallerStructRet, const SmallVectorImpl<ISD::OutputArg> &Outs, const SmallVectorImpl<SDValue> &OutVals, const SmallVectorImpl<ISD::InputArg> &Ins, SelectionDAG& DAG) const argument
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/freebsd-12-stable/contrib/llvm-project/llvm/lib/Target/AMDGPU/ |
H A D | AMDGPUISelLowering.h | 203 const SmallVectorImpl<SDValue> &OutVals, const SDLoc &DL,
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H A D | SIISelLowering.cpp | 2272 const SmallVectorImpl<SDValue> &OutVals, 2279 OutVals, DL, DAG); 2323 SDValue Arg = OutVals[RealRVLocIdx]; 2597 const SmallVectorImpl<SDValue> &OutVals, 2662 return parametersInCSRMatch(MRI, CallerPreserved, ArgLocs, OutVals); 2681 SmallVector<SDValue, 32> &OutVals = CLI.OutVals; local 2728 Callee, CallConv, IsVarArg, Outs, OutVals, Ins, DAG); 2793 SDValue Arg = OutVals[i]; 2985 IsThisReturn ? OutVals[ 2269 LowerReturn(SDValue Chain, CallingConv::ID CallConv, bool isVarArg, const SmallVectorImpl<ISD::OutputArg> &Outs, const SmallVectorImpl<SDValue> &OutVals, const SDLoc &DL, SelectionDAG &DAG) const argument 2594 isEligibleForTailCallOptimization( SDValue Callee, CallingConv::ID CalleeCC, bool IsVarArg, const SmallVectorImpl<ISD::OutputArg> &Outs, const SmallVectorImpl<SDValue> &OutVals, const SmallVectorImpl<ISD::InputArg> &Ins, SelectionDAG &DAG) const argument [all...] |
H A D | AMDGPUISelLowering.cpp | 1020 const SmallVectorImpl<SDValue> &OutVals, 1023 //assert(!isVarArg && Outs.empty() && OutVals.empty() && 1016 LowerReturn( SDValue Chain, CallingConv::ID CallConv, bool isVarArg, const SmallVectorImpl<ISD::OutputArg> &Outs, const SmallVectorImpl<SDValue> &OutVals, const SDLoc &DL, SelectionDAG &DAG) const argument
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/freebsd-12-stable/contrib/llvm-project/llvm/lib/Target/SystemZ/ |
H A D | SystemZISelLowering.h | 520 const SmallVectorImpl<SDValue> &OutVals, const SDLoc &DL,
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H A D | SystemZISelLowering.cpp | 1495 SmallVectorImpl<SDValue> &OutVals = CLI.OutVals; local 1534 SDValue ArgValue = OutVals[I]; 1548 SDValue PartValue = OutVals[I + 1]; 1692 const SmallVectorImpl<SDValue> &OutVals, 1718 SDValue RetValue = OutVals[I]; 1689 LowerReturn(SDValue Chain, CallingConv::ID CallConv, bool IsVarArg, const SmallVectorImpl<ISD::OutputArg> &Outs, const SmallVectorImpl<SDValue> &OutVals, const SDLoc &DL, SelectionDAG &DAG) const argument
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/freebsd-12-stable/contrib/llvm-project/llvm/lib/Target/X86/ |
H A D | X86ISelLowering.h | 1330 const SmallVectorImpl<SDValue> &OutVals, 1407 const SmallVectorImpl<SDValue> &OutVals,
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H A D | X86FastISel.cpp | 3175 auto &OutVals = CLI.OutVals; local 3255 for (int i = 0, e = OutVals.size(); i != e; ++i) { 3256 Value *&Val = OutVals[i]; 3321 const Value *ArgVal = OutVals[VA.getValNo()];
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H A D | X86ISelLowering.cpp | 2641 const SmallVectorImpl<SDValue> &OutVals, 2676 SDValue ValToCopy = OutVals[OutsIndex]; 3783 SmallVectorImpl<SDValue> &OutVals = CLI.OutVals; 3837 Outs, OutVals, Ins, DAG); 3937 SDValue Arg = OutVals[OutIndex]; 4118 SDValue Arg = OutVals[OutsIndex]; 4469 const SmallVectorImpl<SDValue> &OutVals, 4594 SDValue Arg = OutVals[i]; 4636 if (!parametersInCSRMatch(MRI, CallerPreserved, ArgLocs, OutVals)) 2638 LowerReturn(SDValue Chain, CallingConv::ID CallConv, bool isVarArg, const SmallVectorImpl<ISD::OutputArg> &Outs, const SmallVectorImpl<SDValue> &OutVals, const SDLoc &dl, SelectionDAG &DAG) const argument [all...] |
/freebsd-12-stable/contrib/llvm-project/llvm/lib/Target/NVPTX/ |
H A D | NVPTXISelLowering.cpp | 1428 SmallVectorImpl<SDValue> &OutVals = CLI.OutVals; local 1455 // So a different index should be used for indexing into Outs/OutVals. 1519 SDValue StVal = OutVals[OIdx]; 1609 SDValue srcAddr = DAG.getNode(ISD::ADD, dl, PtrVT, OutVals[OIdx], 2664 const SmallVectorImpl<SDValue> &OutVals, 2678 assert(VTs.size() == OutVals.size() && "Bad return value decomposition"); 2698 SDValue RetVal = OutVals[i]; 2661 LowerReturn(SDValue Chain, CallingConv::ID CallConv, bool isVarArg, const SmallVectorImpl<ISD::OutputArg> &Outs, const SmallVectorImpl<SDValue> &OutVals, const SDLoc &dl, SelectionDAG &DAG) const argument
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/freebsd-12-stable/contrib/llvm-project/llvm/lib/Target/Mips/ |
H A D | MipsFastISel.cpp | 1157 const Value *ArgVal = CLI.OutVals[VA.getValNo()]; 1527 OutVTs.reserve(CLI.OutVals.size()); 1529 for (auto *Val : CLI.OutVals) {
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H A D | MipsISelLowering.h | 621 const SmallVectorImpl<SDValue> &OutVals,
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H A D | MipsISelLowering.cpp | 3148 SmallVectorImpl<SDValue> &OutVals = CLI.OutVals; local 3254 SDValue Arg = OutVals[i]; 3779 const SmallVectorImpl<SDValue> &OutVals, 3797 SDValue Val = OutVals[i]; 3776 LowerReturn(SDValue Chain, CallingConv::ID CallConv, bool IsVarArg, const SmallVectorImpl<ISD::OutputArg> &Outs, const SmallVectorImpl<SDValue> &OutVals, const SDLoc &DL, SelectionDAG &DAG) const argument
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/freebsd-12-stable/contrib/llvm-project/llvm/lib/Target/PowerPC/ |
H A D | PPCISelLowering.cpp | 5513 SmallVectorImpl<SDValue> &OutVals = CLI.OutVals; local 5565 isTailCall, isPatchPoint, Outs, OutVals, Ins, 5570 isTailCall, isPatchPoint, Outs, OutVals, Ins, 5575 isTailCall, isPatchPoint, Outs, OutVals, Ins, 5579 isTailCall, isPatchPoint, Outs, OutVals, Ins, 5587 const SmallVectorImpl<SDValue> &OutVals, 5704 SDValue Arg = OutVals[RealArgIdx]; 5840 const SmallVectorImpl<SDValue> &OutVals, 6047 SDValue Arg = OutVals[ 5583 LowerCall_32SVR4( SDValue Chain, SDValue Callee, CallingConv::ID CallConv, bool isVarArg, bool isTailCall, bool isPatchPoint, const SmallVectorImpl<ISD::OutputArg> &Outs, const SmallVectorImpl<SDValue> &OutVals, const SmallVectorImpl<ISD::InputArg> &Ins, const SDLoc &dl, SelectionDAG &DAG, SmallVectorImpl<SDValue> &InVals, ImmutableCallSite CS) const argument 5836 LowerCall_64SVR4( SDValue Chain, SDValue Callee, CallingConv::ID CallConv, bool isVarArg, bool isTailCall, bool isPatchPoint, const SmallVectorImpl<ISD::OutputArg> &Outs, const SmallVectorImpl<SDValue> &OutVals, const SmallVectorImpl<ISD::InputArg> &Ins, const SDLoc &dl, SelectionDAG &DAG, SmallVectorImpl<SDValue> &InVals, ImmutableCallSite CS) const argument 6497 LowerCall_Darwin( SDValue Chain, SDValue Callee, CallingConv::ID CallConv, bool isVarArg, bool isTailCall, bool isPatchPoint, const SmallVectorImpl<ISD::OutputArg> &Outs, const SmallVectorImpl<SDValue> &OutVals, const SmallVectorImpl<ISD::InputArg> &Ins, const SDLoc &dl, SelectionDAG &DAG, SmallVectorImpl<SDValue> &InVals, ImmutableCallSite CS) const argument 7079 LowerCall_AIX( SDValue Chain, SDValue Callee, CallingConv::ID CallConv, bool isVarArg, bool isTailCall, bool isPatchPoint, const SmallVectorImpl<ISD::OutputArg> &Outs, const SmallVectorImpl<SDValue> &OutVals, const SmallVectorImpl<ISD::InputArg> &Ins, const SDLoc &dl, SelectionDAG &DAG, SmallVectorImpl<SDValue> &InVals, ImmutableCallSite CS) const argument 7247 LowerReturn(SDValue Chain, CallingConv::ID CallConv, bool isVarArg, const SmallVectorImpl<ISD::OutputArg> &Outs, const SmallVectorImpl<SDValue> &OutVals, const SDLoc &dl, SelectionDAG &DAG) const argument [all...] |
H A D | PPCFastISel.cpp | 1593 unsigned NumArgs = CLI.OutVals.size(); 1616 Value *ArgValue = CLI.OutVals[i];
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/freebsd-12-stable/contrib/llvm-project/llvm/include/llvm/CodeGen/ |
H A D | TargetLowering.h | 3057 const SmallVectorImpl<SDValue> &OutVals) const; 3475 SmallVector<SDValue, 32> OutVals; member in struct:llvm::TargetLoweringBase::TargetLowering::CallLoweringInfo 3682 const SmallVectorImpl<SDValue> & /*OutVals*/,
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/freebsd-12-stable/contrib/llvm-project/llvm/lib/Target/AArch64/ |
H A D | AArch64ISelLowering.cpp | 3757 const SmallVectorImpl<SDValue> &OutVals, 3865 if (!parametersInCSRMatch(MRI, CallerPreserved, ArgLocs, OutVals)) 3917 SmallVector<SDValue, 32> &OutVals = CLI.OutVals; local 3936 Callee, CallConv, IsVarArg, Outs, OutVals, Ins, DAG); 4058 SDValue Arg = OutVals[i]; 4337 IsThisReturn ? OutVals[0] : SDValue()); 4355 const SmallVectorImpl<SDValue> &OutVals, 4376 SDValue Arg = OutVals[realRVLocIdx]; 3754 isEligibleForTailCallOptimization( SDValue Callee, CallingConv::ID CalleeCC, bool isVarArg, const SmallVectorImpl<ISD::OutputArg> &Outs, const SmallVectorImpl<SDValue> &OutVals, const SmallVectorImpl<ISD::InputArg> &Ins, SelectionDAG &DAG) const argument 4352 LowerReturn(SDValue Chain, CallingConv::ID CallConv, bool isVarArg, const SmallVectorImpl<ISD::OutputArg> &Outs, const SmallVectorImpl<SDValue> &OutVals, const SDLoc &DL, SelectionDAG &DAG) const argument
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H A D | AArch64FastISel.cpp | 3080 const Value *ArgVal = CLI.OutVals[VA.getValNo()]; 3237 OutVTs.reserve(CLI.OutVals.size()); 3239 for (auto *Val : CLI.OutVals) {
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/freebsd-12-stable/contrib/llvm-project/llvm/lib/CodeGen/SelectionDAG/ |
H A D | FastISel.cpp | 1241 CLI.OutVals.push_back(Arg.Val);
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H A D | SelectionDAGBuilder.cpp | 1800 SmallVector<SDValue, 8> OutVals; local 1919 OutVals.push_back(Parts[i]); 1939 OutVals.push_back( 1949 Chain, CallConv, isVarArg, Outs, OutVals, getCurSDLoc(), DAG); 9162 CLI.OutVals.clear(); 9304 CLI.OutVals.push_back(Parts[j]);
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H A D | TargetLowering.cpp | 81 const SmallVectorImpl<SDValue> &OutVals) const { 93 SDValue Value = OutVals[I];
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