Searched refs:MCII (Results 26 - 50 of 75) sorted by relevance

123

/freebsd-12-stable/contrib/llvm-project/llvm/lib/Target/MSP430/MCTargetDesc/
H A DMSP430MCTargetDesc.h33 MCCodeEmitter *createMSP430MCCodeEmitter(const MCInstrInfo &MCII,
/freebsd-12-stable/contrib/llvm-project/llvm/lib/Target/RISCV/MCTargetDesc/
H A DRISCVMCTargetDesc.h35 MCCodeEmitter *createRISCVMCCodeEmitter(const MCInstrInfo &MCII,
H A DRISCVMCCodeEmitter.cpp44 MCInstrInfo const &MCII; member in class:__anon5326::RISCVMCCodeEmitter
47 RISCVMCCodeEmitter(MCContext &ctx, MCInstrInfo const &MCII) argument
48 : Ctx(ctx), MCII(MCII) {}
86 MCCodeEmitter *llvm::createRISCVMCCodeEmitter(const MCInstrInfo &MCII, argument
89 return new RISCVMCCodeEmitter(Ctx, MCII);
179 const MCInstrDesc &Desc = MCII.get(MI.getOpcode());
251 MCInstrDesc const &Desc = MCII.get(MI.getOpcode());
/freebsd-12-stable/contrib/llvm-project/llvm/lib/Target/Sparc/MCTargetDesc/
H A DSparcMCTargetDesc.h35 MCCodeEmitter *createSparcMCCodeEmitter(const MCInstrInfo &MCII,
H A DSparcMCCodeEmitter.cpp46 const MCInstrInfo &MCII; member in class:__anon5344::SparcMCCodeEmitter
51 : MCII(mcii), Ctx(ctx) {}
229 MCCodeEmitter *llvm::createSparcMCCodeEmitter(const MCInstrInfo &MCII, argument
232 return new SparcMCCodeEmitter(MCII, Ctx);
/freebsd-12-stable/contrib/llvm-project/llvm/lib/Target/AMDGPU/MCTargetDesc/
H A DR600MCCodeEmitter.cpp39 const MCInstrInfo &MCII; member in class:__anon4998::R600MCCodeEmitter
43 : MRI(mri), MCII(mcii) {}
93 MCCodeEmitter *llvm::createR600MCCodeEmitter(const MCInstrInfo &MCII, argument
96 return new R600MCCodeEmitter(MCII, MRI);
105 const MCInstrDesc &Desc = MCII.get(MI.getOpcode());
176 if (HAS_NATIVE_OPERANDS(MCII.get(MI.getOpcode()).TSFlags))
H A DSIMCCodeEmitter.cpp89 MCCodeEmitter *llvm::createSIMCCodeEmitter(const MCInstrInfo &MCII, argument
92 return new SIMCCodeEmitter(MCII, MRI, Ctx);
286 const MCInstrDesc &Desc = MCII.get(MI.getOpcode());
381 const MCInstrDesc &Desc = MCII.get(MI.getOpcode());
475 const MCInstrDesc &Desc = MCII.get(MI.getOpcode());
490 const MCInstrDesc &Desc = MCII.get(MI.getOpcode());
/freebsd-12-stable/contrib/llvm-project/llvm/lib/Target/Hexagon/Disassembler/
H A DHexagonDisassembler.cpp45 std::unique_ptr<MCInstrInfo const> const MCII; member in class:__anon5132::HexagonDisassembler::std
50 MCInstrInfo const *MCII)
51 : MCDisassembler(STI, Ctx), MCII(MCII), CurrentBundle(new MCInst *),
65 MCInstrInfo MCII = *Disassembler.MCII; local
67 MI.size() != HexagonMCInstrInfo::getExtendableOp(MCII, MI))
69 unsigned Alignment = HexagonMCInstrInfo::getExtentAlignment(MCII, MI);
188 HexagonMCChecker Checker(getContext(), *MCII, STI, MI,
457 if (HexagonMCInstrInfo::isNewValue(*MCII, M
49 HexagonDisassembler(const MCSubtargetInfo &STI, MCContext &Ctx, MCInstrInfo const *MCII) argument
[all...]
/freebsd-12-stable/contrib/llvm-project/llvm/lib/Target/Hexagon/MCTargetDesc/
H A DHexagonAsmBackend.cpp43 std::unique_ptr <MCInstrInfo> MCII; member in class:__anon5192::HexagonAsmBackend
64 MCII(T.createMCInstrInfo()), RelaxTarget(new MCInst *),
536 const MCInstrDesc &MCID = HexagonMCInstrInfo::getDesc(*MCII, HMI);
539 if (llvm::HexagonMCInstrInfo::getType(*MCII, HMI) == HexagonII::TypeJ ||
540 (llvm::HexagonMCInstrInfo::getType(*MCII, HMI) == HexagonII::TypeCJ &&
542 (llvm::HexagonMCInstrInfo::getType(*MCII, HMI) == HexagonII::TypeNCJ &&
544 (llvm::HexagonMCInstrInfo::getType(*MCII, HMI) == HexagonII::TypeCR &&
546 if (HexagonMCInstrInfo::isExtendable(*MCII, HMI)) {
549 HMI.getOperand(HexagonMCInstrInfo::getExtendableOp(*MCII, HMI));
671 *MCII, CrntHM
[all...]
H A DHexagonMCChecker.h38 MCInstrInfo const &MCII; member in class:llvm::HexagonMCChecker
111 explicit HexagonMCChecker(MCContext &Context, MCInstrInfo const &MCII,
H A DHexagonMCELFStreamer.h21 std::unique_ptr<MCInstrInfo> MCII; member in class:llvm::HexagonMCELFStreamer
H A DHexagonMCTargetDesc.h84 MCCodeEmitter *createHexagonMCCodeEmitter(const MCInstrInfo &MCII,
H A DHexagonMCCompound.cpp348 static bool lookForCompound(MCInstrInfo const &MCII, MCContext &Context, argument
360 if (HexagonMCInstrInfo::getType(MCII, *JumpInst) == HexagonII::TypeJ) {
398 void HexagonMCInstrInfo::tryCompound(MCInstrInfo const &MCII, MCSubtargetInfo const &STI, argument
407 bool StartedValid = llvm::HexagonMCShuffle(Context, false, MCII, STI, MCI);
414 while (lookForCompound(MCII, Context, CheckList)) {
422 !llvm::HexagonMCShuffle(Context, false, MCII, STI, MCI)) {
H A DHexagonMCELFStreamer.cpp52 MCII(createHexagonMCInstrInfo()) {}
59 MCII(createHexagonMCInstrInfo()) {}
/freebsd-12-stable/contrib/llvm-project/llvm/lib/Target/WebAssembly/Disassembler/
H A DWebAssemblyDisassembler.cpp44 std::unique_ptr<const MCInstrInfo> MCII; member in class:__anon5378::final
55 std::unique_ptr<const MCInstrInfo> MCII)
56 : MCDisassembler(STI, Ctx), MCII(std::move(MCII)) {}
63 std::unique_ptr<const MCInstrInfo> MCII(T.createMCInstrInfo());
64 return new WebAssemblyDisassembler(STI, Ctx, std::move(MCII));
54 WebAssemblyDisassembler(const MCSubtargetInfo &STI, MCContext &Ctx, std::unique_ptr<const MCInstrInfo> MCII) argument
/freebsd-12-stable/contrib/llvm-project/llvm/lib/Target/ARM/MCTargetDesc/
H A DARMMCTargetDesc.h59 MCCodeEmitter *createARMLEMCCodeEmitter(const MCInstrInfo &MCII,
63 MCCodeEmitter *createARMBEMCCodeEmitter(const MCInstrInfo &MCII,
/freebsd-12-stable/contrib/llvm-project/llvm/lib/Target/PowerPC/MCTargetDesc/
H A DPPCMCCodeEmitter.h26 const MCInstrInfo &MCII; member in class:llvm::PPCMCCodeEmitter
32 : MCII(mcii), CTX(ctx),
/freebsd-12-stable/contrib/llvm-project/llvm/lib/Target/WebAssembly/MCTargetDesc/
H A DWebAssemblyMCTargetDesc.cpp64 static MCCodeEmitter *createCodeEmitter(const MCInstrInfo &MCII, argument
67 return createWebAssemblyMCCodeEmitter(MCII);
/freebsd-12-stable/contrib/llvm-project/llvm/lib/Target/AArch64/MCTargetDesc/
H A DAArch64MCTargetDesc.h39 MCCodeEmitter *createAArch64MCCodeEmitter(const MCInstrInfo &MCII,
/freebsd-12-stable/contrib/llvm-project/llvm/lib/Target/SystemZ/MCTargetDesc/
H A DSystemZMCTargetDesc.h84 MCCodeEmitter *createSystemZMCCodeEmitter(const MCInstrInfo &MCII,
/freebsd-12-stable/contrib/llvm-project/llvm/lib/Target/X86/MCTargetDesc/
H A DX86AsmBackend.cpp114 std::unique_ptr<const MCInstrInfo> MCII; member in class:__anon5415::X86AsmBackend
129 MCII(T.createMCInstrInfo()) {
286 const MCInstrInfo &MCII) {
292 const MCInstrDesc &Desc = MCII.get(Opcode);
300 classifySecondInstInMacroFusion(const MCInst &MI, const MCInstrInfo &MCII) { argument
301 X86::CondCode CC = getCondFromBranch(MI, MCII);
306 static bool isRIPRelative(const MCInst &MI, const MCInstrInfo &MCII) { argument
308 const MCInstrDesc &Desc = MCII.get(Opcode);
321 const MCInstrInfo &MCII) {
323 if (isRIPRelative(Inst, MCII))
285 getCondFromBranch(const MCInst &MI, const MCInstrInfo &MCII) argument
320 isFirstMacroFusibleInst(const MCInst &Inst, const MCInstrInfo &MCII) argument
[all...]
/freebsd-12-stable/contrib/llvm-project/llvm/include/llvm/MC/
H A DMCSchedule.h358 int computeInstrLatency(const MCSubtargetInfo &STI, const MCInstrInfo &MCII,
370 getReciprocalThroughput(const MCSubtargetInfo &STI, const MCInstrInfo &MCII,
/freebsd-12-stable/contrib/llvm-project/llvm/lib/Target/AMDGPU/Disassembler/
H A DAMDGPUDisassembler.h42 std::unique_ptr<MCInstrInfo const> const MCII; member in class:llvm::AMDGPUDisassembler::std
51 MCInstrInfo const *MCII);
/freebsd-12-stable/contrib/llvm-project/llvm/tools/llvm-mca/
H A Dllvm-mca.cpp373 std::unique_ptr<MCInstrInfo> MCII(TheTarget->createMCInstrInfo());
376 TheTarget->createMCInstrAnalysis(MCII.get()));
379 mca::AsmCodeRegionGenerator CRG(*TheTarget, SrcMgr, Ctx, *MAI, *STI, *MCII);
413 Triple(TripleName), AssemblerDialect, *MAI, *MCII, *MRI));
430 mca::InstrBuilder IB(*STI, *MCII, *MRI, MCIA.get());
443 TheTarget->createMCCodeEmitter(*MCII, *MRI, Ctx));
503 *STI, *MCII, CE, ShowEncoding, Insts, *IP));
530 *STI, *MCII, CE, ShowEncoding, Insts, *IP));
/freebsd-12-stable/contrib/llvm-project/llvm/lib/Object/
H A DModuleSymbolTable.cpp96 std::unique_ptr<MCInstrInfo> MCII(T->createMCInstrInfo());
97 if (!MCII)
114 T->createMCAsmParser(*STI, *Parser, *MCII, MCOptions));

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