| /freebsd-12-stable/contrib/llvm-project/llvm/include/llvm/CodeGen/ |
| H A D | LiveIntervals.h | 477 LaneBitmask LaneMask);
481 /// Only full operands or operands with subregisters matching \p LaneMask
487 LaneBitmask LaneMask = LaneBitmask::getAll());
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| /freebsd-12-stable/contrib/llvm-project/llvm/lib/Target/Hexagon/ |
| H A D | HexagonBlockRanges.cpp | 240 if (I.LaneMask.all() || (I.LaneMask.any() && !S.isValid())) {
246 if ((I.LaneMask & TRI.getSubRegIndexLaneMask(SI)).any())
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| H A D | HexagonExpandCondsets.cpp | 356 KillAt(I->end, S.LaneMask);
531 updateDeadsInRange(Reg, S.LaneMask, S);
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| /freebsd-12-stable/contrib/llvm-project/llvm/lib/CodeGen/ |
| H A D | LiveRegMatrix.cpp | 88 if ((S.LaneMask & Mask).any()) {
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| H A D | SplitKit.h | 432 /// \p InsertBefore. This can be invoked with a \p LaneMask which may make it
434 SlotIndex buildCopy(unsigned FromReg, unsigned ToReg, LaneBitmask LaneMask,
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| H A D | LivePhysRegs.cpp | 156 LaneBitmask Mask = LI.LaneMask;
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| H A D | MIRPrinter.cpp | 677 if (!LI.LaneMask.all())
678 OS << ":0x" << PrintLaneMask(LI.LaneMask);
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| H A D | RegisterScavenging.cpp | 53 void RegScavenger::setRegUsed(Register Reg, LaneBitmask LaneMask) { argument
54 LiveUnits.addRegMasked(Reg, LaneMask);
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| H A D | LiveRangeCalc.cpp | 121 SubLRC.extendToUses(S, Reg, S.LaneMask, &LI);
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| H A D | DetectDeadLanes.cpp | 259 MO1UsedLanes = RC->LaneMask;
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| H A D | RDFLiveness.cpp | 813 LV.push_back(RegisterRef(I->PhysReg, I->LaneMask));
867 if ((M & I.LaneMask).any())
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| H A D | MachineScheduler.cpp | 1111 bool Decrement = P.LaneMask.any();
1123 << PrintLaneMask(P.LaneMask) << ' ' << *SU.getInstr();
1127 assert(P.LaneMask.any());
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| H A D | BranchFolding.cpp | 385 assert(P.LaneMask == LaneBitmask::getAll() &&
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| H A D | RDFGraph.cpp | 903 LiveIns.insert(RegisterRef(I.PhysReg, I.LaneMask));
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| /freebsd-12-stable/contrib/llvm-project/llvm/lib/Target/AMDGPU/ |
| H A D | GCNRegPressure.h | 234 LiveRegMap[SII.getInstructionFromIndex(SI)][Reg] |= S.LaneMask;
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| H A D | SIRegisterInfo.cpp | 1862 if ((S.LaneMask & SubLanes) == SubLanes) {
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| /freebsd-12-stable/contrib/llvm-project/llvm/utils/TableGen/ |
| H A D | CodeGenRegisters.h | 72 mutable LaneBitmask LaneMask; member in class:llvm::CodeGenSubRegIndex
132 // Compute LaneMask from Composed. Return LaneMask.
335 LaneBitmask LaneMask; member in class:llvm::CodeGenRegisterClass
783 // LaneMask is contained in CoveringLanes will be completely covered by
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| H A D | RegisterInfoEmitter.cpp | 826 << "::composeSubRegIndexLaneMaskImpl(unsigned IdxA, LaneBitmask LaneMask)"
832 " LaneBitmask::Type M = LaneMask.getAsInteger() & Ops->Mask.getAsInteger();\n"
843 " LaneBitmask LaneMask) const {\n"
844 " LaneMask &= getSubRegIndexLaneMask(IdxA);\n"
849 " LaneBitmask::Type M = LaneMask.getAsInteger();\n"
1259 printMask(OS << " ", Idx.LaneMask);
1405 printMask(OS, RC.LaneMask);
1634 OS << "\tLaneMask: " << PrintLaneMask(RC.LaneMask) << '\n';
1659 OS << "\tLaneMask: " << PrintLaneMask(SRI.LaneMask) << '\n';
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| /freebsd-12-stable/contrib/llvm-project/llvm/lib/IR/ |
| H A D | AutoUpgrade.cpp | 2327 unsigned LaneMask = (Imm >> (l * NumControlBits)) & ControlBitsMask; local
2330 LaneMask += NumLanes;
2332 ShuffleMask.push_back(LaneMask * NumElementsInLane + i);
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| /freebsd-12-stable/contrib/llvm-project/llvm/lib/Target/AArch64/ |
| H A D | AArch64ISelLowering.cpp | 6718 int *LaneMask = &Mask[i * ResMultiplier]; local
6723 LaneMask[j] = ExtractBase + j;
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| /freebsd-12-stable/contrib/llvm-project/llvm/lib/Target/X86/ |
| H A D | X86ISelLowering.cpp | 14910 auto &LaneMask = (i & 1) ? RHSMask : LHSMask;
14911 LaneMask[LaneBase + (M & 1)] = M;
14955 SmallVector<int, 16> LaneMask(NumElts, SM_SentinelUndef);
14960 LaneMask[(DstLane * NumEltsPerLane) + j] =
14980 SDValue LanePermute = DAG.getVectorShuffle(VT, DL, V1, V2, LaneMask);
[all...] |
| /freebsd-12-stable/contrib/llvm-project/llvm/lib/Target/ARM/ |
| H A D | ARMISelLowering.cpp | 7561 int *LaneMask = &Mask[i * ResMultiplier]; local
7566 LaneMask[j] = ExtractBase + j;
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