Searched refs:WRITE4 (Results 26 - 50 of 50) sorted by relevance

12

/freebsd-11.0-release/sys/dev/beri/virtio/
H A Dvirtio.h39 #define WRITE4(_sc, _reg, _val) \ macro
H A Dvirtio_block.c302 WRITE4(sc, VIRTIO_MMIO_INTERRUPT_STATUS, reg);
379 WRITE4(sc, VIRTIO_MMIO_DEVICE_ID, reg);
383 WRITE4(sc, VIRTIO_MMIO_QUEUE_NUM_MAX, reg);
389 WRITE4(sc, VIRTIO_MMIO_HOST_FEATURES, reg);
400 WRITE4(sc, VIRTIO_MMIO_CONFIG + i, *s);
/freebsd-11.0-release/sys/dev/hatm/
H A Dif_hatmvar.h476 #define WRITE4(SC,OFF,VAL) bus_space_write_4(SC->memt, SC->memh, (OFF), (VAL)) macro
488 #define WRITE_SUNI(SC,OFF,VAL) WRITE4(SC, HE_REGO_SUNI + 4 * (OFF), (VAL))
492 WRITE4(SC, HE_REGO_LB_MEM_ADDR, (OFF)); \
493 WRITE4(SC, HE_REGO_LB_MEM_ACCESS, \
501 WRITE4(SC, HE_REGO_LB_MEM_ADDR, (OFF)); \
502 WRITE4(SC, HE_REGO_LB_MEM_DATA, (VAL)); \
503 WRITE4(SC, HE_REGO_LB_MEM_ACCESS, \
511 WRITE4(SC, HE_REGO_CON_DAT, (VAL)); \
512 WRITE4(SC, HE_REGO_CON_CTL, \
520 WRITE4(S
[all...]
H A Dif_hatm_intr.c169 WRITE4(sc, HE_REGO_TBRQ_H(group), q->head << 2);
407 WRITE4(sc, HE_REGO_RBP_T(large, group),
528 WRITE4(sc, HE_REGO_RBRQ_H(group), rq->head << 3);
561 WRITE4(sc, HE_REGO_INT_FIFO, HE_REGM_INT_FIFO_CLRA);
720 WRITE4(sc, HE_REGO_IRQ_HEAD(0),
H A Dif_hatm_tx.c222 WRITE4(sc, HE_REGO_TPDRQ_T, (sc->tpdrq.tail << HE_REGS_TPDRQ_T_T));
/freebsd-11.0-release/sys/arm/freescale/imx/
H A Dimx_gpio.c67 #define WRITE4(_sc, _r, _v) \ macro
72 WRITE4((_sc), (_r), READ4((_sc), (_r)) | (_m))
74 WRITE4((_sc), (_r), READ4((_sc), (_r)) & ~(_m))
300 WRITE4(sc, IMX_GPIO_ISR_REG, (1U << gi->gi_irq));
372 WRITE4(sc, reg, wrk);
374 WRITE4(sc, IMX_GPIO_ISR_REG, (1u << irq));
426 WRITE4(sc, IMX_GPIO_ISR_REG, (1U << irq));
440 WRITE4(sc, IMX_GPIO_ISR_REG, (1U << irq));
664 WRITE4(sc, IMX_GPIO_DR_REG,
710 WRITE4(s
[all...]
H A Dimx6_ssi.c66 #define WRITE4(_sc, _reg, _val) \ macro
531 WRITE4(sc, SSI_SIER, reg);
548 WRITE4(sc, SSI_SIER, reg);
685 WRITE4(sc, SSI_STCCR, reg);
690 WRITE4(sc, SSI_SFCSR, reg);
703 WRITE4(sc, SSI_STCR, reg);
710 WRITE4(sc, SSI_SCR, reg);
/freebsd-11.0-release/sys/dev/agp/
H A Dagp_ati.c59 #define WRITE4(off,v) bus_space_write_4(sc->bst, sc->bsh, off, v) macro
233 WRITE4(ATI_GART_FEATURE_ID, 0x00060000);
238 WRITE4(ATI_GART_BASE, sc->ag_pdir);
259 WRITE4(ATI_GART_BASE, 0);
347 WRITE4(ATI_GART_CACHE_CNTRL, 1);
H A Dagp_amd.c59 #define WRITE4(off,v) bus_space_write_4(sc->bst, sc->bsh, off, v) macro
253 WRITE4(AGP_AMD751_ATTBASE, gatt->ag_pdir);
288 WRITE4(AGP_AMD751_ATTBASE, 0);
371 WRITE4(AGP_AMD751_TLBCTRL, 1);
/freebsd-11.0-release/sys/arm/freescale/vybrid/
H A Dvf_sai.c361 WRITE4(sc, I2S_TCR2, reg);
626 WRITE4(sc, I2S_TCSR, reg);
630 WRITE4(sc, I2S_TCR3, reg);
633 WRITE4(sc, I2S_TCR1, reg);
639 WRITE4(sc, I2S_TCR2, reg);
645 WRITE4(sc, I2S_TCR3, reg);
654 WRITE4(sc, I2S_TCR4, reg);
663 WRITE4(sc, I2S_TCR5, reg);
669 WRITE4(sc, I2S_TCSR, reg);
H A Dvf_ccm.c381 WRITE4(sc, clk->sel_reg, reg);
388 WRITE4(sc, clk->reg, reg);
463 WRITE4(sc, CCM_CCR, reg);
477 WRITE4(sc, CCM_CCGR(i), 0xffffffff);
H A Dvf_gpio.c284 WRITE4(sc, GPIO_PTOR(i), (1 << (i % 32)));
308 WRITE4(sc, GPIO_PCOR(pin->gp_pin),
354 WRITE4(sc, GPIO_PSOR(i), (1 << (i % 32)));
356 WRITE4(sc, GPIO_PCOR(i), (1 << (i % 32)));
H A Dvf_tcon.c83 WRITE4(tcon_sc, TCON0_CTRL1, TCON_BYPASS);
H A Dvf_edma.c200 WRITE4(sc, DMA_ERQ, reg);
247 WRITE4(sc, DMA_ERQ, reg);
252 WRITE4(sc, DMA_EEI, reg);
H A Dvf_src.c95 WRITE4(src_sc, SRC_SCR, SW_RST);
H A Dvf_port.c122 WRITE4(sc, PORT_PCR(i), reg);
179 WRITE4(sc, PORT_PCR(pnum), reg);
H A Dvf_iomuxc.c161 WRITE4(sc, IOMUXC(pin), pin_cfg);
/freebsd-11.0-release/sys/dev/fatm/
H A Dif_fatm.c193 WRITE4(sc, q->q.card + FATMOC_GETOC3_BUF, 0);
195 WRITE4(sc, q->q.card + FATMOC_OP,
282 WRITE4(sc, q->q.card + FATMOC_GETOC3_BUF, sc->reg_mem.paddr);
284 WRITE4(sc, q->q.card + FATMOC_OP,
382 WRITE4(sc, FATMO_HIMR, 1);
420 WRITE4(sc, FATMO_APP_BASE, FATMO_COMMON_ORIGIN);
423 WRITE4(sc, FATMO_UART_TO_960, XMIT_READY);
426 WRITE4(sc, FATMO_UART_TO_HOST, XMIT_READY);
429 WRITE4(sc, FATMO_BOOT_STATUS, COLD_START);
580 WRITE4(s
[all...]
H A Dif_fatmvar.h326 #define WRITE4(SC, OFF, VAL) bus_space_write_4(SC->memt, SC->memh, OFF, VAL) macro
/freebsd-11.0-release/sys/arm/altera/socfpga/
H A Dsocfpga_rstmgr.c164 WRITE4(sc, RSTMGR_BRGMODRST, reg);
180 WRITE4(sc, RSTMGR_CTRL,
H A Dsocfpga_gpio.c71 #define WRITE4(_sc, _reg, _val) \ macro
343 WRITE4(sc, GPIO_SWPORTA_DR, reg);
374 WRITE4(sc, GPIO_SWPORTA_DDR, reg);
422 WRITE4(sc, GPIO_SWPORTA_DR, reg);
/freebsd-11.0-release/sys/dev/beri/virtio/network/
H A Dif_vtbe.c95 #define WRITE4(_sc, _reg, _val) \ macro
222 WRITE4(sc, VIRTIO_MMIO_INTERRUPT_STATUS, reg);
456 WRITE4(sc, VIRTIO_MMIO_INTERRUPT_STATUS, reg);
593 WRITE4(sc, VIRTIO_MMIO_DEVICE_ID, reg);
597 WRITE4(sc, VIRTIO_MMIO_QUEUE_NUM_MAX, reg);
602 WRITE4(sc, VIRTIO_MMIO_HOST_FEATURES, reg);
/freebsd-11.0-release/sys/arm/samsung/exynos/
H A Dexynos5_pad.c83 #define WRITE4(_sc, _port, _reg, _val) \ macro
392 WRITE4(sc, sc->gpio_map[i].port, sc->gpio_map[i].pend, reg);
446 WRITE4(sc, bank.port, bank.con, reg);
461 WRITE4(sc, bank.port, bank.ext_con, reg);
466 WRITE4(sc, bank.port, bank.mask, reg);
729 WRITE4(sc, bank.port, bank.con + 0x4, reg);
766 WRITE4(sc, bank.port, bank.con, reg);
771 WRITE4(sc, bank.port, bank.con, reg);
825 WRITE4(sc, bank.port, bank.con + 0x4, reg);
H A Dexynos5_combiner.c350 WRITE4(sc, IESR(n), reg);
/freebsd-11.0-release/sys/dev/beri/
H A Dberi_ring.c66 #define WRITE4(_sc, _reg, _val) \ macro
144 WRITE4(sc, offset + 0, ((uint32_t *)src)[0]);
145 WRITE4(sc, offset + 4, ((uint32_t *)src)[1]);

Completed in 144 milliseconds

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