Searched refs:ROTR (Results 26 - 34 of 34) sorted by relevance
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| /freebsd-11.0-release/contrib/llvm/lib/CodeGen/SelectionDAG/ |
| H A D | DAGCombiner.cpp | 1388 case ISD::ROTR:
3566 if (TLI.isOperationLegalOrCustom(ISD::ROTR, VT))
3567 return DAG.getNode(ISD::ROTR, DL, VT, BSwap, ShAmt);
3977 bool HasROTR = TLI.isOperationLegalOrCustom(ISD::ROTR, VT);
4018 SDValue Rot = DAG.getNode(HasROTL ? ISD::ROTL : ISD::ROTR, DL, VT,
4066 LExtOp0, RExtOp0, ISD::ROTL, ISD::ROTR, DL);
4071 RExtOp0, LExtOp0, ISD::ROTR, ISD::ROTL, DL);
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| H A D | LegalizeDAG.cpp | 1361 case ISD::ROTR:
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| /freebsd-11.0-release/contrib/llvm/lib/Target/Mips/AsmParser/ |
| H A D | MipsAsmParser.cpp | 3319 emitRRI(Mips::ROTR, DReg, SReg, ShiftValue, Inst.getLoc(), Instructions);
3324 emitRRI(Mips::ROTR, DReg, SReg, ImmValue, Inst.getLoc(), Instructions);
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| /freebsd-11.0-release/contrib/llvm/lib/Target/SystemZ/ |
| H A D | SystemZISelLowering.cpp | 189 setOperationAction(ISD::ROTR, VT, Expand);
329 // At present ROTL isn't matched by DAGCombiner. ROTR should be
332 setOperationAction(ISD::ROTR, VT, Expand);
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| /freebsd-11.0-release/contrib/llvm/lib/Target/AArch64/ |
| H A D | AArch64ISelDAGToDAG.cpp | 322 case ISD::ROTR:
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| H A D | AArch64ISelLowering.cpp | 220 setOperationAction(ISD::ROTR, VT, Expand);
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| /freebsd-11.0-release/contrib/llvm/lib/Target/PowerPC/ |
| H A D | PPCISelLowering.cpp | 225 // PowerPC does not have ROTR
226 setOperationAction(ISD::ROTR, MVT::i32 , Expand);
227 setOperationAction(ISD::ROTR, MVT::i64 , Expand);
488 setOperationAction(ISD::ROTR, VT, Expand);
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| /freebsd-11.0-release/contrib/llvm/lib/Target/ARM/ |
| H A D | ARMISelLowering.cpp | 754 setOperationAction(ISD::ROTR, VT, Expand);
10381 return DAG.getNode(ISD::ROTR, SDLoc(N), VT, N0, N1);
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| /freebsd-11.0-release/contrib/llvm/lib/Target/X86/ |
| H A D | X86ISelLowering.cpp | 736 setOperationAction(ISD::ROTR, VT, Expand);
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