Searched refs:MI (Results 226 - 250 of 562) sorted by relevance

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/freebsd-11.0-release/contrib/llvm/lib/Target/PowerPC/
H A DPPCVSXCopy.cpp95 MachineInstr *MI = I; local
96 if (!MI->isFullCopy())
99 MachineOperand &DstMO = MI->getOperand(0);
100 MachineOperand &SrcMO = MI->getOperand(1);
117 BuildMI(MBB, MI, MI->getDebugLoc(),
143 BuildMI(MBB, MI, MI->getDebugLoc(),
/freebsd-11.0-release/contrib/llvm/tools/lldb/tools/lldb-mi/
H A DMICmdInterpreter.h21 // Details: MI command interpreter. It takes text data from the MI driver
23 // matches Machine Interface (MI) format and commands defined in the
24 // MI application.
27 class CMICmdInterpreter : public CMICmnBase, public MI::ISingleton<CMICmdInterpreter>
29 friend MI::ISingleton<CMICmdInterpreter>;
H A DMICmdMgr.h28 // Details: MI command manager. Oversees command operations, controls command
34 class CMICmdMgr : public CMICmnBase, public MI::ISingleton<CMICmdMgr>
36 friend class MI::ISingleton<CMICmdMgr>;
/freebsd-11.0-release/contrib/llvm/lib/CodeGen/
H A DAggressiveAntiDepBreaker.cpp183 void AggressiveAntiDepBreaker::Observe(MachineInstr *MI, unsigned Count, argument
188 GetPassthruRegs(MI, PassthruRegs);
189 PrescanInstruction(MI, Count, PassthruRegs);
190 ScanInstruction(MI, Count);
193 DEBUG(MI->dump());
217 bool AggressiveAntiDepBreaker::IsImplicitDefUse(MachineInstr *MI,
229 Op = MI->findRegisterUseOperand(Reg, true);
231 Op = MI->findRegisterDefOperand(Reg);
236 void AggressiveAntiDepBreaker::GetPassthruRegs(MachineInstr *MI,
238 for (unsigned i = 0, e = MI
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H A DCriticalAntiDepBreaker.h87 void Observe(MachineInstr *MI, unsigned Count,
94 void PrescanInstruction(MachineInstr *MI);
95 void ScanInstruction(MachineInstr *MI, unsigned Count);
H A DExpandISelPseudos.cpp56 MachineInstr *MI = MBBI++; local
58 // If MI is a pseudo, expand it.
59 if (MI->usesCustomInsertionHook()) {
62 TLI->EmitInstrWithCustomInserter(MI, MBB);
H A DScheduleDAGInstrs.cpp47 cl::desc("Enable use of AA during MI DAG construction"));
50 cl::init(true), cl::desc("Enable use of TBAA during MI DAG construction"));
130 static void getUnderlyingObjectsForInstr(const MachineInstr *MI, argument
134 if (!MI->hasOneMemOperand() ||
135 (!(*MI->memoperands_begin())->getValue() &&
136 !(*MI->memoperands_begin())->getPseudoValue()) ||
137 (*MI->memoperands_begin())->isVolatile())
141 (*MI->memoperands_begin())->getPseudoValue()) {
159 const Value *V = (*MI->memoperands_begin())->getValue();
291 MachineInstr *MI local
386 MachineInstr *MI = SU->getInstr(); local
495 const MachineInstr *MI = SU->getInstr(); local
519 isGlobalMemoryObject(AliasAnalysis *AA, MachineInstr *MI) argument
527 isUnsafeMemoryObject(MachineInstr *MI, const MachineFrameInfo *MFI, const DataLayout &DL) argument
756 MachineInstr *MI = I; local
798 const MachineInstr *MI = SU->getInstr(); local
885 MachineInstr *MI = std::prev(MII); local
1192 toggleBundleKillFlag(MachineInstr *MI, unsigned Reg, bool NewKillState) argument
1229 toggleKillFlag(MachineInstr *MI, MachineOperand &MO) argument
1278 MachineInstr *MI = --I; local
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H A DAggressiveAntiDepBreaker.h147 void Observe(MachineInstr *MI, unsigned Count,
158 /// that is both implicitly used and defined in MI
159 bool IsImplicitDefUse(MachineInstr *MI, MachineOperand& MO);
161 /// If MI implicitly def/uses a register, then
163 void GetPassthruRegs(MachineInstr *MI, std::set<unsigned>& PassthruRegs);
169 void PrescanInstruction(MachineInstr *MI, unsigned Count,
171 void ScanInstruction(MachineInstr *MI, unsigned Count);
/freebsd-11.0-release/contrib/llvm/lib/Target/ARM/
H A DARMInstrInfo.h42 void expandLoadStackGuard(MachineBasicBlock::iterator MI,
/freebsd-11.0-release/contrib/llvm/lib/Target/BPF/
H A DBPFRegisterInfo.h32 void eliminateFrameIndex(MachineBasicBlock::iterator MI, int SPAdj,
/freebsd-11.0-release/contrib/llvm/lib/Target/Hexagon/MCTargetDesc/
H A DHexagonMCCodeEmitter.cpp67 void HexagonMCCodeEmitter::encodeInstruction(MCInst const &MI, raw_ostream &OS, argument
70 MCInst &HMB = const_cast<MCInst &>(MI);
76 *CurrentBundle = &MI;
93 const MCInst &MI, raw_ostream &OS, SmallVectorImpl<MCFixup> &Fixups,
95 MCInst HMB = MI;
254 static Hexagon::Fixups getFixupNoBits(MCInstrInfo const &MCII, const MCInst &MI, argument
257 const MCInstrDesc &MCID = HexagonMCInstrInfo::getDesc(MCII, MI);
258 unsigned insnType = llvm::HexagonMCInstrInfo::getType(MCII, MI);
341 switch (HexagonMCInstrInfo::getAccessSize(MCII, MI)) {
391 unsigned HexagonMCCodeEmitter::getExprOpValue(const MCInst &MI, argument
92 EncodeSingleInstruction( const MCInst &MI, raw_ostream &OS, SmallVectorImpl<MCFixup> &Fixups, const MCSubtargetInfo &STI, uint32_t Parse, size_t Index) const argument
722 getMachineOpValue(MCInst const &MI, MCOperand const &MO, SmallVectorImpl<MCFixup> &Fixups, MCSubtargetInfo const &STI) const argument
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H A DHexagonMCShuffler.cpp37 MCInst *MI = const_cast<MCInst *>(I.getInst()); local
39 if (!HexagonMCInstrInfo::isImmext(*MI)) {
40 append(MI, Extender, HexagonMCInstrInfo::getUnits(MCII, STI, *MI),
44 Extender = MI;
61 MCInst *MI = const_cast<MCInst *>(I.getInst()); local
62 if (!HexagonMCInstrInfo::isImmext(*MI)) {
63 append(MI, Extender, HexagonMCInstrInfo::getUnits(MCII, STI, *MI),
67 Extender = MI;
83 MCInst const *MI = I->getDesc(); local
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/freebsd-11.0-release/contrib/llvm/include/llvm/ADT/
H A DEquivalenceClasses.h46 /// for (EquivalenceClasses<int>::member_iterator MI = EC.member_begin(I);
47 /// MI != EC.member_end(); ++MI) // Loop over members in this set.
48 /// cerr << *MI << " "; // Print member.
127 member_iterator MI = RHS.member_begin(I); local
128 member_iterator LeaderIt = member_begin(insert(*MI));
129 for (++MI; MI != member_end(); ++MI)
130 unionSets(LeaderIt, member_begin(insert(*MI)));
167 member_iterator MI = findLeader(V); local
176 member_iterator MI = findLeader(insert(V)); local
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H A DUniqueVector.h61 typename std::map<T, unsigned>::const_iterator MI = Map.find(Entry); local
64 if (MI != Map.end()) return MI->second;
/freebsd-11.0-release/contrib/llvm/lib/Target/AMDGPU/
H A DSIFixControlFlowLiveIntervals.cpp71 for (const MachineInstr &MI : MBB) {
72 switch (MI.getOpcode()) {
79 unsigned Reg = MI.getOperand(0).getReg();
H A DR600MachineScheduler.cpp185 isPhysicalRegCopy(MachineInstr *MI) { argument
186 if (MI->getOpcode() != AMDGPU::COPY)
189 return !TargetRegisterInfo::isVirtualRegister(MI->getOperand(1).getReg());
223 MachineInstr *MI = SU->getInstr(); local
225 if (TII->isTransOnly(MI))
228 switch (MI->getOpcode()) {
237 if (MI->getOperand(1).isUndef()) {
238 // MI will become a KILL, don't considers it in scheduling
248 if(TII->isVector(*MI) ||
249 TII->isCubeOp(MI
359 AssignSlot(MachineInstr* MI, unsigned Slot) argument
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/freebsd-11.0-release/contrib/llvm/lib/Target/Hexagon/
H A DHexagonBitTracker.h29 bool evaluate(const MachineInstr *MI, const CellMapType &Inputs,
41 bool evaluateLoad(const MachineInstr *MI, const CellMapType &Inputs,
43 bool evaluateFormalCopy(const MachineInstr *MI, const CellMapType &Inputs,
H A DHexagonRegisterInfo.cpp124 MachineInstr &MI = *II; local
125 MachineBasicBlock &MB = *MI.getParent();
132 int FI = MI.getOperand(FIOp).getIndex();
137 int RealOffset = Offset + MI.getOperand(FIOp+1).getImm();
139 unsigned Opc = MI.getOpcode();
142 MI.setDesc(HII.get(Hexagon::A2_addi));
143 MI.getOperand(FIOp).ChangeToImmediate(RealOffset);
144 MI.RemoveOperand(FIOp+1);
148 MI.setDesc(HII.get(Hexagon::A2_addi));
153 MI
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H A DRDFCopy.cpp29 void CopyPropagation::recordCopy(NodeAddr<StmtNode*> SA, MachineInstr *MI) { argument
30 assert(MI->getOpcode() == TargetOpcode::COPY);
31 const MachineOperand &Op0 = MI->getOperand(0), &Op1 = MI->getOperand(1);
77 MachineInstr *MI = SA.Addr->getCode(); local
78 if (MI->isCopy())
79 recordCopy(SA, MI);
148 MachineInstr *MI = NodeAddr<StmtNode*>(IA).Addr->getCode(); local
169 if (MI->isCopy()) {
170 MachineOperand &Op0 = MI
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H A DRDFDeadCode.cpp29 bool DeadCodeElimination::isLiveInstr(const MachineInstr *MI) const {
30 if (MI->mayStore() || MI->isBranch() || MI->isCall() || MI->isReturn())
32 if (MI->hasOrderedMemoryRef() || MI->hasUnmodeledSideEffects())
34 if (MI->isPHI())
36 for (auto &Op : MI->operands())
198 MachineInstr *MI local
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H A DHexagonGenPredicate.cpp95 bool isConvertibleToPredForm(const MachineInstr *MI);
99 bool convertToPredForm(MachineInstr *MI);
165 bool HexagonGenPredicate::isConvertibleToPredForm(const MachineInstr *MI) { argument
166 unsigned Opc = MI->getOpcode();
177 if (MI->getOperand(2).isImm() && MI->getOperand(2).getImm() == 0)
189 MachineInstr *MI = &*I; local
190 unsigned Opc = MI->getOpcode();
194 if (isPredReg(MI->getOperand(1).getReg())) {
195 Register RD = MI
350 convertToPredForm(MachineInstr *MI) argument
351 DEBUG(dbgs() << LLVM_FUNCTION_NAME << ": " << MI << " " << *MI); local
502 MachineInstr *MI = *I; local
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H A DHexagonRDFOpt.cpp125 MachineInstr *MI = NodeAddr<StmtNode*>(IA).Addr->getCode(); local
127 auto getOpNum = [MI] (MachineOperand &Op) -> unsigned {
128 for (unsigned i = 0, n = MI->getNumOperands(); i != n; ++i)
129 if (&MI->getOperand(i) == &Op)
138 MI->RemoveOperand(OpNum);
143 RA.Addr->setRegRef(&MI->getOperand(N));
145 RA.Addr->setRegRef(&MI->getOperand(N-1));
154 MachineInstr *MI = NodeAddr<StmtNode*>(IA).Addr->getCode(); local
156 if (HII.getAddrMode(MI) != HexagonII::PostInc)
158 unsigned Opc = MI
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/freebsd-11.0-release/contrib/llvm/lib/Target/XCore/
H A DXCoreInstrInfo.cpp64 XCoreInstrInfo::isLoadFromStackSlot(const MachineInstr *MI, int &FrameIndex) const{ argument
65 int Opcode = MI->getOpcode();
68 if ((MI->getOperand(1).isFI()) && // is a stack slot
69 (MI->getOperand(2).isImm()) && // the imm is zero
70 (isZeroImm(MI->getOperand(2))))
72 FrameIndex = MI->getOperand(1).getIndex();
73 return MI->getOperand(0).getReg();
85 XCoreInstrInfo::isStoreToStackSlot(const MachineInstr *MI, argument
87 int Opcode = MI->getOpcode();
90 if ((MI
429 loadImmediate( MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, unsigned Reg, uint64_t Value) const argument
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/freebsd-11.0-release/contrib/llvm/include/llvm/CodeGen/
H A DRegisterPressure.h156 /// Analyze the given instruction \p MI and fill in the Uses, Defs and
158 void collect(const MachineInstr &MI, const TargetRegisterInfo &TRI,
163 void detectDeadDefs(const MachineInstr &MI, const LiveIntervals &LIS);
192 /// Store the effects of a change in pressure on things that MI scheduler cares
348 /// Get the MI position corresponding to this register pressure.
351 // Reset the MI position corresponding to the register pressure. This allows
408 void getMaxUpwardPressureDelta(const MachineInstr *MI,
414 void getUpwardPressureDelta(const MachineInstr *MI,
424 void getMaxDownwardPressureDelta(const MachineInstr *MI,
432 void getMaxPressureDelta(const MachineInstr *MI,
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/freebsd-11.0-release/contrib/llvm/tools/clang/lib/StaticAnalyzer/Checkers/
H A DCheckObjCInstMethSignature.cpp107 MapTy::iterator MI = IMeths.find(S); local
109 if (MI == IMeths.end() || MI->second == nullptr)
113 ObjCMethodDecl *MethDerived = MI->second;
114 MI->second = nullptr;

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