Searched refs:Ins (Results 51 - 60 of 60) sorted by relevance

123

/freebsd-11.0-release/contrib/llvm/lib/CodeGen/SelectionDAG/
H A DSelectionDAGBuilder.cpp7023 CLI.Ins.clear();
7083 CLI.Ins.push_back(MyFlags);
7210 assert((CLI.IsTailCall || InVals.size() == CLI.Ins.size()) &&
7222 DEBUG(for (unsigned i = 0, e = CLI.Ins.size(); i != e; ++i) {
7225 assert(EVT(CLI.Ins[i].VT) == InVals[i].getValueType() &&
7351 SmallVector<ISD::InputArg, 16> Ins;
7366 Ins.push_back(RetArg);
7445 Ins.push_back(MyFlags);
7448 Ins[Ins
[all...]
H A DFastISel.cpp941 CLI.Ins.push_back(MyFlags);
/freebsd-11.0-release/contrib/llvm/lib/Target/ARM/
H A DARMISelLowering.cpp1426 const SmallVectorImpl<ISD::InputArg> &Ins,
1435 CCInfo.AnalyzeCallResult(Ins,
1562 SmallVectorImpl<ISD::InputArg> &Ins = CLI.Ins; local
1584 Outs, OutVals, Ins, DAG);
1680 assert(!Ins.empty() && Ins[0].VT == MVT::i32 &&
1960 if (!Ins.empty())
1965 return LowerCallResult(Chain, InFlag, CallConv, isVarArg, Ins, dl, DAG,
2083 const SmallVectorImpl<ISD::InputArg> &Ins,
1424 LowerCallResult(SDValue Chain, SDValue InFlag, CallingConv::ID CallConv, bool isVarArg, const SmallVectorImpl<ISD::InputArg> &Ins, SDLoc dl, SelectionDAG &DAG, SmallVectorImpl<SDValue> &InVals, bool isThisReturn, SDValue ThisVal) const argument
2076 IsEligibleForTailCallOptimization(SDValue Callee, CallingConv::ID CalleeCC, bool isVarArg, bool isCalleeStructRet, bool isCallerStructRet, const SmallVectorImpl<ISD::OutputArg> &Outs, const SmallVectorImpl<SDValue> &OutVals, const SmallVectorImpl<ISD::InputArg> &Ins, SelectionDAG& DAG) const argument
3141 LowerFormalArguments(SDValue Chain, CallingConv::ID CallConv, bool isVarArg, const SmallVectorImpl<ISD::InputArg> &Ins, SDLoc dl, SelectionDAG &DAG, SmallVectorImpl<SDValue> &InVals) const argument
[all...]
/freebsd-11.0-release/contrib/llvm/utils/TableGen/
H A DCodeGenRegisters.cpp322 DenseMap<const CodeGenRegister*, CodeGenSubRegIndex*>::iterator Ins = local
324 if (Ins->second == SI->first)
332 SI->first->getName() + " and " + Ins->second->getName());
H A DDAGISelMatcherGen.cpp135 const TreePatternNode *GetInstPatternNode(const DAGInstruction &Ins,
/freebsd-11.0-release/contrib/llvm/lib/Target/SystemZ/
H A DSystemZISelLowering.cpp789 static void VerifyVectorTypes(const SmallVectorImpl<ISD::InputArg> &Ins) { argument
790 for (unsigned i = 0; i < Ins.size(); ++i)
791 VerifyVectorType(Ins[i].VT, Ins[i].ArgVT);
861 const SmallVectorImpl<ISD::InputArg> &Ins,
874 VerifyVectorTypes(Ins);
879 CCInfo.AnalyzeFormalArguments(Ins, CC_SystemZ);
1013 SmallVectorImpl<ISD::InputArg> &Ins = CLI.Ins; local
1025 VerifyVectorTypes(Ins);
860 LowerFormalArguments(SDValue Chain, CallingConv::ID CallConv, bool IsVarArg, const SmallVectorImpl<ISD::InputArg> &Ins, SDLoc DL, SelectionDAG &DAG, SmallVectorImpl<SDValue> &InVals) const argument
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/freebsd-11.0-release/contrib/llvm/lib/Target/AMDGPU/
H A DR600ISelLowering.cpp1642 const SmallVectorImpl<ISD::InputArg> &Ins,
1653 getOriginalFunctionArgs(DAG, MF.getFunction(), Ins, LocalIns);
1657 for (unsigned i = 0, e = Ins.size(); i < e; ++i) {
1659 const ISD::InputArg &In = Ins[i];
1638 LowerFormalArguments( SDValue Chain, CallingConv::ID CallConv, bool isVarArg, const SmallVectorImpl<ISD::InputArg> &Ins, SDLoc DL, SelectionDAG &DAG, SmallVectorImpl<SDValue> &InVals) const argument
/freebsd-11.0-release/contrib/llvm/lib/Target/X86/
H A DX86FastISel.cpp2835 auto &Ins = CLI.Ins; local
3169 CCRetInfo.AnalyzeCallResult(Ins, RetCC_X86);
3180 ((Is64Bit || Ins[i].Flags.isInReg()) && !Subtarget->hasSSE1())) {
H A DX86ISelLowering.cpp2398 const SmallVectorImpl<ISD::InputArg> &Ins,
2407 CCInfo.AnalyzeCallResult(Ins, RetCC_X86);
2416 ((Is64Bit || Ins[i].Flags.isInReg()) && !Subtarget->hasSSE1())) {
2480 argsAreStructReturn(const SmallVectorImpl<ISD::InputArg> &Ins, bool IsMCU) { argument
2481 if (Ins.empty())
2484 const ISD::ArgFlagsTy &Flags = Ins[0].Flags;
2554 const SmallVectorImpl<ISD::InputArg> &Ins,
2560 ISD::ArgFlagsTy Flags = Ins[i].Flags;
2586 Offset = (Subtarget.is64Bit() ? 8 : 4) * ((i + 1) % Ins.size() - 1);
2670 const SmallVectorImpl<ISD::InputArg> &Ins, SDLo
2396 LowerCallResult(SDValue Chain, SDValue InFlag, CallingConv::ID CallConv, bool isVarArg, const SmallVectorImpl<ISD::InputArg> &Ins, SDLoc dl, SelectionDAG &DAG, SmallVectorImpl<SDValue> &InVals) const argument
2552 LowerMemArgument(SDValue Chain, CallingConv::ID CallConv, const SmallVectorImpl<ISD::InputArg> &Ins, SDLoc dl, SelectionDAG &DAG, const CCValAssign &VA, MachineFrameInfo *MFI, unsigned i) const argument
2668 LowerFormalArguments( SDValue Chain, CallingConv::ID CallConv, bool isVarArg, const SmallVectorImpl<ISD::InputArg> &Ins, SDLoc dl, SelectionDAG &DAG, SmallVectorImpl<SDValue> &InVals) const argument
3074 SmallVectorImpl<ISD::InputArg> &Ins = CLI.Ins; local
3690 IsEligibleForTailCallOptimization( SDValue Callee, CallingConv::ID CalleeCC, bool isVarArg, bool isCalleeStructRet, bool isCallerStructRet, Type *RetTy, const SmallVectorImpl<ISD::OutputArg> &Outs, const SmallVectorImpl<SDValue> &OutVals, const SmallVectorImpl<ISD::InputArg> &Ins, SelectionDAG &DAG) const argument
[all...]
/freebsd-11.0-release/contrib/llvm/include/llvm/Target/
H A DTargetLowering.h2301 /// described by the Ins array, into the specified DAG. The implementation
2308 const SmallVectorImpl<ISD::InputArg> &/*Ins*/,
2363 SmallVector<ISD::InputArg, 32> Ins;
2470 /// and the values to be returned by the call are described by the Ins

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