Searched refs:FS (Results 26 - 50 of 196) sorted by relevance

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/freebsd-11.0-release/contrib/llvm/tools/clang/include/clang/Basic/
H A DFileSystemStatCache.h73 vfs::FileSystem &FS);
97 vfs::FileSystem &FS) = 0;
100 std::unique_ptr<vfs::File> *F, vfs::FileSystem &FS) {
102 return Next->getStat(Path, Data, isFile, F, FS);
106 return get(Path, Data, isFile, F, nullptr, FS) ? CacheMissing : CacheExists;
126 vfs::FileSystem &FS) override;
99 statChained(const char *Path, FileData &Data, bool isFile, std::unique_ptr<vfs::File> *F, vfs::FileSystem &FS) argument
/freebsd-11.0-release/contrib/llvm/lib/Target/XCore/
H A DXCoreSubtarget.h44 const std::string &FS, const TargetMachine &TM);
48 void ParseSubtargetFeatures(StringRef CPU, StringRef FS);
H A DXCoreTargetMachine.cpp26 StringRef CPU, StringRef FS,
32 TT, CPU, FS, Options, RM, CM, OL),
34 Subtarget(TT, CPU, FS, *this) {
25 XCoreTargetMachine(const Target &T, const Triple &TT, StringRef CPU, StringRef FS, const TargetOptions &Options, Reloc::Model RM, CodeModel::Model CM, CodeGenOpt::Level OL) argument
/freebsd-11.0-release/contrib/llvm/lib/Target/BPF/
H A DBPFSubtarget.h41 BPFSubtarget(const Triple &TT, const std::string &CPU, const std::string &FS,
46 void ParseSubtargetFeatures(StringRef CPU, StringRef FS);
H A DBPFTargetMachine.cpp40 StringRef CPU, StringRef FS,
44 : LLVMTargetMachine(T, computeDataLayout(TT), TT, CPU, FS, Options, RM, CM,
47 Subtarget(TT, CPU, FS, *this) {
39 BPFTargetMachine(const Target &T, const Triple &TT, StringRef CPU, StringRef FS, const TargetOptions &Options, Reloc::Model RM, CodeModel::Model CM, CodeGenOpt::Level OL) argument
/freebsd-11.0-release/contrib/llvm/lib/Target/
H A DTargetSubtargetInfo.cpp23 const Triple &TT, StringRef CPU, StringRef FS,
28 : MCSubtargetInfo(TT, CPU, FS, PF, PD, ProcSched, WPR, WL, RA, IS, OC, FP) {
22 TargetSubtargetInfo( const Triple &TT, StringRef CPU, StringRef FS, ArrayRef<SubtargetFeatureKV> PF, ArrayRef<SubtargetFeatureKV> PD, const SubtargetInfoKV *ProcSched, const MCWriteProcResEntry *WPR, const MCWriteLatencyEntry *WL, const MCReadAdvanceEntry *RA, const InstrStage *IS, const unsigned *OC, const unsigned *FP) argument
/freebsd-11.0-release/usr.bin/hexdump/
H A Dhexdump.c51 FS *fshead; /* head of format strings */
59 FS *tfs;
/freebsd-11.0-release/contrib/llvm/lib/Target/Sparc/
H A DSparcTargetMachine.h28 StringRef FS, const TargetOptions &Options,
50 StringRef FS, const TargetOptions &Options,
61 StringRef FS, const TargetOptions &Options,
71 StringRef FS, const TargetOptions &Options,
H A DSparcSubtarget.h47 const std::string &FS, TargetMachine &TM, bool is64bit);
75 void ParseSubtargetFeatures(StringRef CPU, StringRef FS);
76 SparcSubtarget &initializeSubtargetDependencies(StringRef CPU, StringRef FS);
/freebsd-11.0-release/contrib/ntp/include/
H A Dascii.h69 #define FS 28 macro
/freebsd-11.0-release/contrib/gcc/config/rs6000/
H A Daix.h217 /* If the current unwind info (FS) does not contain explicit info
224 #define MD_FROB_UPDATE_CONTEXT(CTX, FS) \
226 if ((FS)->regs.reg[2].how == REG_UNSAVED) \
236 #define MD_FROB_UPDATE_CONTEXT(CTX, FS) \
238 if ((FS)->regs.reg[2].how == REG_UNSAVED) \
/freebsd-11.0-release/contrib/llvm/lib/Target/AArch64/
H A DAArch64TargetMachine.h31 StringRef FS, const TargetOptions &Options,
58 StringRef FS, const TargetOptions &Options,
69 StringRef FS, const TargetOptions &Options,
H A DAArch64Subtarget.cpp40 AArch64Subtarget::initializeSubtargetDependencies(StringRef FS) { argument
46 ParseSubtargetFeatures(CPUString, FS);
51 const std::string &FS,
53 : AArch64GenSubtargetInfo(TT, CPU, FS), ARMProcFamily(Others),
59 InstrInfo(initializeSubtargetDependencies(FS)), TSInfo(),
50 AArch64Subtarget(const Triple &TT, const std::string &CPU, const std::string &FS, const TargetMachine &TM, bool LittleEndian) argument
/freebsd-11.0-release/contrib/llvm/lib/Target/AMDGPU/
H A DAMDGPUTargetMachine.h40 AMDGPUTargetMachine(const Target &T, const Triple &TT, StringRef FS,
66 R600TargetMachine(const Target &T, const Triple &TT, StringRef FS,
80 GCNTargetMachine(const Target &T, const Triple &TT, StringRef FS,
H A DAMDGPUSubtarget.cpp37 StringRef GPU, StringRef FS) {
50 FullFS += FS;
67 AMDGPUSubtarget::AMDGPUSubtarget(const Triple &TT, StringRef GPU, StringRef FS, argument
69 : AMDGPUGenSubtargetInfo(TT, GPU, FS), DevName(GPU), Is64bit(false),
84 initializeSubtargetDependencies(TT, GPU, FS);
36 initializeSubtargetDependencies(const Triple &TT, StringRef GPU, StringRef FS) argument
/freebsd-11.0-release/contrib/llvm/lib/Target/NVPTX/
H A DNVPTXSubtarget.h56 const std::string &FS, const NVPTXTargetMachine &TM);
102 NVPTXSubtarget &initializeSubtargetDependencies(StringRef CPU, StringRef FS);
103 void ParseSubtargetFeatures(StringRef CPU, StringRef FS);
/freebsd-11.0-release/contrib/llvm/lib/Target/SystemZ/
H A DSystemZSubtarget.h57 StringRef FS);
60 const std::string &FS, const TargetMachine &TM);
80 void ParseSubtargetFeatures(StringRef CPU, StringRef FS);
/freebsd-11.0-release/contrib/llvm/include/llvm/MC/
H A DMCSubtargetInfo.h45 FeatureBitset FeatureBits; // Feature bits for current CPU + FS
53 MCSubtargetInfo(const Triple &TT, StringRef CPU, StringRef FS,
86 void InitMCProcessorInfo(StringRef CPU, StringRef FS);
91 void setDefaultFeatures(StringRef CPU, StringRef FS);
103 FeatureBitset ToggleFeature(StringRef FS);
107 FeatureBitset ApplyFeatureFlag(StringRef FS);
/freebsd-11.0-release/contrib/llvm/lib/Target/ARM/
H A DARMTargetMachine.cpp177 StringRef CPU, StringRef FS,
182 CPU, FS, Options, RM, CM, OL),
185 Subtarget(TT, CPU, FS, *this, isLittle), isLittle(isLittle) {
212 std::string FS = !FSAttr.hasAttribute(Attribute::None) local
227 FS += FS.empty() ? "+soft-float" : ",+soft-float";
229 auto &I = SubtargetMap[CPU + FS];
235 I = llvm::make_unique<ARMSubtarget>(TargetTriple, CPU, FS, *this, isLittle);
249 StringRef CPU, StringRef FS,
253 : ARMBaseTargetMachine(T, TT, CPU, FS, Option
176 ARMBaseTargetMachine(const Target &T, const Triple &TT, StringRef CPU, StringRef FS, const TargetOptions &Options, Reloc::Model RM, CodeModel::Model CM, CodeGenOpt::Level OL, bool isLittle) argument
[all...]
H A DARMSubtarget.cpp73 StringRef FS) {
75 initSubtargetFeatures(CPU, FS);
80 StringRef FS) {
81 ARMSubtarget &STI = initializeSubtargetDependencies(CPU, FS);
89 const std::string &FS,
91 : ARMGenSubtargetInfo(TT, CPU, FS), ARMProcFamily(Others),
94 FrameLowering(initializeFrameLowering(CPU, FS)),
168 void ARMSubtarget::initSubtargetFeatures(StringRef CPU, StringRef FS) { argument
188 if (!FS.empty()) {
190 ArchFS = (Twine(ArchFS) + "," + FS)
72 initializeSubtargetDependencies(StringRef CPU, StringRef FS) argument
79 initializeFrameLowering(StringRef CPU, StringRef FS) argument
88 ARMSubtarget(const Triple &TT, const std::string &CPU, const std::string &FS, const ARMBaseTargetMachine &TM, bool IsLittle) argument
[all...]
H A DARMTargetMachine.h41 StringRef FS, const TargetOptions &Options,
67 StringRef FS, const TargetOptions &Options, Reloc::Model RM,
77 StringRef FS, const TargetOptions &Options,
88 StringRef FS, const TargetOptions &Options,
101 StringRef FS, const TargetOptions &Options,
112 StringRef FS, const TargetOptions &Options,
123 StringRef FS, const TargetOptions &Options,
/freebsd-11.0-release/contrib/llvm/lib/Target/Hexagon/
H A DHexagonSubtarget.cpp63 HexagonSubtarget::initializeSubtargetDependencies(StringRef CPU, StringRef FS) { argument
81 ParseSubtargetFeatures(CPUString, FS);
92 StringRef FS, const TargetMachine &TM)
93 : HexagonGenSubtargetInfo(TT, CPU, FS), CPUString(CPU),
94 InstrInfo(initializeSubtargetDependencies(CPU, FS)), TLInfo(TM, *this),
91 HexagonSubtarget(const Triple &TT, StringRef CPU, StringRef FS, const TargetMachine &TM) argument
/freebsd-11.0-release/contrib/llvm/lib/Target/WebAssembly/
H A DWebAssemblyTargetMachine.cpp45 const Target &T, const Triple &TT, StringRef CPU, StringRef FS,
51 TT, CPU, FS, Options, RM, CM, OL),
76 std::string FS = !FSAttr.hasAttribute(Attribute::None) local
80 auto &I = SubtargetMap[CPU + FS];
86 I = llvm::make_unique<WebAssemblySubtarget>(TargetTriple, CPU, FS, *this);
44 WebAssemblyTargetMachine( const Target &T, const Triple &TT, StringRef CPU, StringRef FS, const TargetOptions &Options, Reloc::Model RM, CodeModel::Model CM, CodeGenOpt::Level OL) argument
/freebsd-11.0-release/contrib/llvm/lib/Target/PowerPC/
H A DPPCSubtarget.cpp44 StringRef FS) {
46 initSubtargetFeatures(CPU, FS);
51 const std::string &FS, const PPCTargetMachine &TM)
52 : PPCGenSubtargetInfo(TT, CPU, FS), TargetTriple(TT),
55 TM(TM), FrameLowering(initializeSubtargetDependencies(CPU, FS)),
108 void PPCSubtarget::initSubtargetFeatures(StringRef CPU, StringRef FS) { argument
123 ParseSubtargetFeatures(CPUName, FS);
43 initializeSubtargetDependencies(StringRef CPU, StringRef FS) argument
50 PPCSubtarget(const Triple &TT, const std::string &CPU, const std::string &FS, const PPCTargetMachine &TM) argument
H A DPPCTargetMachine.cpp113 static std::string computeFSAdditions(StringRef FS, CodeGenOpt::Level OL, argument
115 std::string FullFS = FS;
180 StringRef CPU, StringRef FS,
185 computeFSAdditions(FS, OL, TT), Options, RM, CM, OL),
188 Subtarget(TargetTriple, CPU, computeFSAdditions(FS, OL, TT), *this) {
215 StringRef CPU, StringRef FS,
219 : PPCTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL) {}
224 StringRef CPU, StringRef FS,
228 : PPCTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL) {}
238 std::string FS local
179 PPCTargetMachine(const Target &T, const Triple &TT, StringRef CPU, StringRef FS, const TargetOptions &Options, Reloc::Model RM, CodeModel::Model CM, CodeGenOpt::Level OL) argument
214 PPC32TargetMachine(const Target &T, const Triple &TT, StringRef CPU, StringRef FS, const TargetOptions &Options, Reloc::Model RM, CodeModel::Model CM, CodeGenOpt::Level OL) argument
223 PPC64TargetMachine(const Target &T, const Triple &TT, StringRef CPU, StringRef FS, const TargetOptions &Options, Reloc::Model RM, CodeModel::Model CM, CodeGenOpt::Level OL) argument
[all...]

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