Searched refs:x3 (Results 201 - 225 of 1182) sorted by relevance

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/freebsd-11-stable/sys/arm/nvidia/
H A Dtegra_usbphy.c108 #define UTMIP_XCVR_LSFSLEW(x) (((x) & 0x3) << 10)
109 #define UTMIP_XCVR_LSRSLEW(x) (((x) & 0x3) << 8)
110 #define UTMIP_XCVR_FSSLEW(x) (((x) & 0x3) << 6)
111 #define UTMIP_XCVR_HSSLEW(x) (((x) & 0x3) << 4)
132 #define UTMIP_VBUS_LEVEL_LEVEL(x) (((x) & 0x3) << 8)
133 #define UTMIP_SESS_LEVEL_LEVEL(x) (((x) & 0x3) << 6)
134 #define UTMIP_HSCHIRP_LEVEL(x) (((x) & 0x3) << 4)
135 #define UTMIP_HSDISCON_LEVEL(x) (((x) & 0x3) << 2)
136 #define UTMIP_HSSQUELCH_LEVEL(x) (((x) & 0x3) << 0)
140 #define UTMIP_KEEP_PATT_ON_ACTIVE(x) (((x) & 0x3) << 3
[all...]
/freebsd-11-stable/sys/arm/allwinner/clk/
H A Daw_pll.c58 #define A10_PLL1_OUT_EXT_DIVP (0x3 << 16)
62 #define A10_PLL1_FACTOR_K (0x3 << 4)
64 #define A10_PLL1_FACTOR_M (0x3 << 0)
84 #define A10_PLL5_OUT_EXT_DIVP (0x3 << 16)
88 #define A10_PLL5_FACTOR_K (0x3 << 4)
90 #define A10_PLL5_FACTOR_M1 (0x3 << 2)
92 #define A10_PLL5_FACTOR_M (0x3 << 0)
99 #define A10_PLL6_FACTOR_K (0x3 << 4)
101 #define A10_PLL6_FACTOR_M (0x3 << 0)
115 #define A23_PLL1_FACTOR_K (0x3 <<
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H A Daw_cpusclk.c52 #define A80_CPUS_CLK_SRC_SEL (0x3 << 16)
60 #define A80_CPUS_CLK_RATIO (0x3 << 4)
63 #define A83T_CPUS_CLK_SRC_SEL (0x3 << 16)
71 #define A83T_CPUS_CLK_RATIO (0x3 << 4)
H A Daw_hdmiclk.c54 #define CLK_SRC_SEL (0x3 << 24)
56 #define CLK_SRC_SEL_MAX 0x3
57 #define CLK_RATIO_N (0x3 << 16)
59 #define CLK_RATIO_N_MAX 0x3
/freebsd-11-stable/sys/dev/ixgbe/
H A Dixgbe_phy.h45 #define IXGBE_SFF_IDENTIFIER_SFP 0x3
50 #define IXGBE_SFF_10GBE_COMP_CODES 0x3
85 #define IXGBE_I2C_EEPROM_STATUS_MASK 0x3
89 #define IXGBE_I2C_EEPROM_STATUS_IN_PROGRESS 0x3
/freebsd-11-stable/sys/contrib/ck/include/
H A Dck_pflock.h51 #define CK_PFLOCK_WBITS 0x3 /* Writer bits in reader. */
/freebsd-11-stable/sys/dev/ioat/
H A Dioat_hw.h88 #define IOAT_CHANSTS_HALTED 0x3
/freebsd-11-stable/sys/dev/mlx5/
H A Dport.h39 MLX5_MODULE_ID_SFP = 0x3,
62 #define MLX5_EEPROM_HIGH_PAGE 0x3
64 #define MLX5_EEPROM_INFO_BYTES 0x3
78 #define MLX5_ETH_MODULE_SFF_8436 0x3
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/BPF/Disassembler/
H A DBPFDisassembler.cpp40 BPF_STX = 0x3,
51 BPF_DW = 0x3
58 BPF_MEM = 0x3,
73 uint8_t getInstSize(uint64_t Inst) const { return (Inst >> 59) & 0x3; };
/freebsd-11-stable/include/
H A Ddlfcn.h42 #define RTLD_MODEMASK 0x3
/freebsd-11-stable/usr.sbin/bhyve/
H A Dpci_xhci.h116 #define XHCI_SCTX_2_TT_THINK_TIME_SET(x) (((x) & 0x3) << 16)
117 #define XHCI_SCTX_2_TT_THINK_TIME_GET(x) (((x) >> 16) & 0x3)
135 #define XHCI_EPCTX_0_MULT_SET(x) (((x) & 0x3) << 8)
136 #define XHCI_EPCTX_0_MULT_GET(x) (((x) >> 8) & 0x3)
144 #define XHCI_EPCTX_1_CERR_SET(x) (((x) & 0x3) << 1)
145 #define XHCI_EPCTX_1_CERR_GET(x) (((x) >> 1) & 0x3)
208 #define XHCI_SCTX_0_SCT_PRIM_SSA_16 0x3
/freebsd-11-stable/sys/dev/mlx5/mlx5_fpga/
H A Dmlx5_ifc_fpga.h45 MLX5_FPGA_CAP_SANDBOX_PRODUCT_ID_TLS = 0x3,
132 MLX5_FPGA_CTRL_OPERATION_FLASH_SELECT = 0x3,
158 MLX5_FPGA_ERROR_EVENT_SYNDROME_INTERNAL_LINK_ERROR = 0x3,
213 u8 prio[0x3];
232 u8 rnr_retry[0x3];
234 u8 retry_count[0x3];
468 MLX5_FPGA_SHELL_QP_PACKET_TYPE_DDR_WRITE_RESPONSE = 0x3,
/freebsd-11-stable/sys/contrib/dev/ath/ath_hal/ar9300/
H A Dar9300_aic.c169 aic_atten_word[1] = (0x3 & 0xf)<<14 | (0x1f & 0x1f)<<9 | (0x2 & 0xf)<<5 |
175 aic_atten_word[4] = (0x3 & 0xf)<<14 | (0x1e & 0x1f)<<9 | (0x2 & 0xf)<<5 |
181 aic_atten_word[7] = (0x3 & 0xf)<<14 | (0xf & 0x1f)<<9 | (0x2 & 0xf)<<5 |
187 aic_atten_word[10] =(0x3 & 0xf)<<14 | (0x7 & 0x1f)<<9 | (0x2 & 0xf)<<5 |
193 aic_atten_word[13] =(0x3 & 0xf)<<14 | (0x3 & 0x1f)<<9 | (0x2 & 0xf)<<5 |
194 (0x3 & 0x1f); // -27 dB: 4'd3, 5'd03, -26 dB: 4'd2, 5'd03;
195 aic_atten_word[14] =(0x5 & 0xf)<<14 | (0x3 & 0x1f)<<9 | (0x4 & 0xf)<<5 |
196 (0x3 & 0x1f); // -29 dB: 4'd5, 5'd03, -28 dB: 4'd4, 5'd03;
199 aic_atten_word[16] =(0x3
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/freebsd-11-stable/sys/dev/qlnx/qlnxe/
H A Drdma_common.h94 #define RDMA_CQE_RESPONDER_TYPE_MASK 0x3 /* (use enum rdma_cqe_type) */
102 #define RDMA_CQE_RESPONDER_RESERVED2_MASK 0x3
119 #define RDMA_CQE_REQUESTER_TYPE_MASK 0x3 /* (use enum rdma_cqe_type) */
134 #define RDMA_CQE_COMMON_TYPE_MASK 0x3 /* (use enum rdma_cqe_type) */
315 #define RDMA_SQ_ATOMIC_WQE_RESERVED0_MASK 0x3
525 #define RDMA_SQ_FMR_WQE_RESERVED0_MASK 0x3
603 #define RDMA_SQ_FMR_WQE_1ST_RESERVED0_MASK 0x3
692 #define RDMA_SQ_LOCAL_INV_WQE_RESERVED0_MASK 0x3
830 #define RDMA_SQ_SEND_WQE_RESERVED0_MASK 0x3
938 #define RDMA_PWM_VAL32_DATA_AGG_CMD_MASK 0x3 /* aggregativ
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/freebsd-11-stable/sys/contrib/octeon-sdk/
H A Dcvmx-pip.h673 int bit = cvmx_wqe_get_port(work) & 0x3;
699 bit_loc = 7 - (bsel_pos.s.pos0 & 0x3);
703 bit_loc = 7 - (bsel_pos.s.pos1 & 0x3);
707 bit_loc = 7 - (bsel_pos.s.pos2 & 0x3);
711 bit_loc = 7 - (bsel_pos.s.pos3 & 0x3);
715 bit_loc = 7 - (bsel_pos.s.pos4 & 0x3);
719 bit_loc = 7 - (bsel_pos.s.pos5 & 0x3);
723 bit_loc = 7 - (bsel_pos.s.pos6 & 0x3);
727 bit_loc = 7 - (bsel_pos.s.pos7 & 0x3);
784 int bit = port & 0x3;
[all...]
/freebsd-11-stable/sys/dev/nxge/include/
H A Dxgehal-ring.h44 #define XGE_HAL_RXD_T_CODE_PARITY_ABORT 0x3
71 #define XGE_HAL_RXD_MASK_FRAME_TYPE vBIT(0x3,25,2)
74 (u8)(0x3 & ((control_1 & XGE_HAL_RXD_MASK_FRAME_TYPE) >> 37))
99 XGE_HAL_FRAME_TYPE_IPX = 0x3,
226 #define XGE_HAL_RXD_HASH_TYPE_IPV4 0x3
/freebsd-11-stable/sys/mips/atheros/
H A Dar71xxreg.h253 #define AR71XX_REV_ID_MINOR_MASK 0x3
257 #define AR71XX_REV_ID_REVISION_MASK 0x3
261 #define AR724X_REV_ID_REVISION_MASK 0x3
264 #define AR91XX_REV_ID_MINOR_MASK 0x3
267 #define AR91XX_REV_ID_REVISION_MASK 0x3
/freebsd-11-stable/sys/arm/ti/am335x/
H A Dam335x_prcm.c510 while ((prcm_read_4(clk_details->clkctrl_reg) & 0x3) != 2)
563 while ((prcm_read_4(clk_details->clkctrl_reg) & 0x3) != 0)
606 while ((prcm_read_4(clk_details->clksel_reg) & 0x3) != reg)
628 switch ((ctrl_status>>22) & 0x3) {
641 case 0x3:
780 while ((prcm_read_4(CM_PER_USB0_CLKCTRL) & 0x3) != 2)
807 while ((prcm_read_4(CM_PER_LCDC_CLKCTRL) & 0x3) != 2)
829 while ((prcm_read_4(CM_PER_PRUSS_CLKCTRL) & 0x3) != 2)
849 while ((prcm_read_4(CLKSEL_PRUSS_OCP_CLK) & 0x3) != 0)
/freebsd-11-stable/contrib/apr/encoding/
H A Dapr_encode.c237 *bufout++ = base[ENCODE_TO_ASCII((((src[i]) & 0x3) << 4)
246 *bufout++ = base[ENCODE_TO_ASCII((((src[i]) & 0x3) << 4))];
252 *bufout++ = base[ENCODE_TO_ASCII((((src[i]) & 0x3) << 4)
299 *bufout++ = base[((src[i] & 0x3) << 4)
308 *bufout++ = base[((src[i] & 0x3) << 4)];
314 *bufout++ = base[((src[i] & 0x3) << 4)
593 | ((src[i + 1] >> 6) & 0x3))];
619 | ((src[i + 1] >> 6) & 0x3))];
631 | ((src[i + 1] >> 6) & 0x3))];
644 | ((src[i + 1] >> 6) & 0x3))];
[all...]
/freebsd-11-stable/contrib/binutils/include/opcode/
H A Dmips.h117 #define OP_MASK_COP1CMP 0x3
155 #define OP_MASK_DSPACC 0x3
157 #define OP_MASK_DSPACC_S 0x3
175 #define OP_MASK_BP 0x3
183 #define OP_MASK_MTACC_T 0x3
185 #define OP_MASK_MTACC_D 0x3
/freebsd-11-stable/sys/arm/samsung/exynos/
H A Dexynos5_fimd.c121 #define VSYNC_PULSE_WIDTH_VAL 0x3
123 #define V_FRONT_PORCH_VAL 0x3
125 #define V_BACK_PORCH_VAL 0x3
128 #define HSYNC_PULSE_WIDTH_VAL 0x3
130 #define H_FRONT_PORCH_VAL 0x3
132 #define H_BACK_PORCH_VAL 0x3
/freebsd-11-stable/lib/msun/ld128/
H A Dk_expl.h103 0x1.0163da9fb33356d84a66aep0L, 0x3.36dcdfa4003ec04c360be2404078p-92L,
119 0x1.18af9388c8de9bbbf70b9ap0L, 0x3.c2505c97c0102e5f1211941d2840p-92L,
129 0x1.284dfe1f5638096cf15cf0p0L, 0x3.ca0967fdaa2e52d7c8106f2e262cp-92L,
134 0x1.306fe0a31b7152de8d5a46p0L, 0x3.05c85edecbc27343629f502f1af2p-92L,
137 0x1.356c55f929ff0c94623476p0L, 0x3.73af38d6d8d6f9506c9bbc93cbc0p-92L,
160 0x1.5e76f15ad21486e9be4c20p0L, 0x3.99766a06548a05829e853bdb2b52p-92L,
/freebsd-11-stable/secure/lib/libcrypto/aarch64/
H A Daesv8-armx.S20 mov x3,#-1
25 mov x3,#-2
33 adr x3,rcon
39 ld1 {v1.4s,v2.4s},[x3],#32
63 ld1 {v1.4s},[x3]
172 mov x3,#0
175 mov x0,x3 // return value
289 ldr w5,[x3,#240]
294 ld1 {v16.4s-v17.4s},[x3] // load key schedule...
296 add x7,x3,x
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/freebsd-11-stable/sys/dev/ixl/
H A Di40e_register.h203 #define I40E_PFCM_LANCTXCTL_QUEUE_TYPE_MASK I40E_MASK(0x3, I40E_PFCM_LANCTXCTL_QUEUE_TYPE_SHIFT)
205 #define I40E_PFCM_LANCTXCTL_OP_CODE_MASK I40E_MASK(0x3, I40E_PFCM_LANCTXCTL_OP_CODE_SHIFT)
243 #define I40E_PRTDCB_FCCFG_TFCE_MASK I40E_MASK(0x3, I40E_PRTDCB_FCCFG_TFCE_SHIFT)
255 #define I40E_PRTDCB_GENC_RESERVED_1_MASK I40E_MASK(0x3, I40E_PRTDCB_GENC_RESERVED_1_SHIFT)
402 #define I40E_GLGEN_CLKSTAT_U_CLK_SPEED_MASK I40E_MASK(0x3, I40E_GLGEN_CLKSTAT_U_CLK_SPEED_SHIFT)
414 #define I40E_GLGEN_GPIO_CTL_PRT_NUM_MASK I40E_MASK(0x3, I40E_GLGEN_GPIO_CTL_PRT_NUM_SHIFT)
432 #define I40E_GLGEN_GPIO_CTL_INT_MODE_MASK I40E_MASK(0x3, I40E_GLGEN_GPIO_CTL_INT_MODE_SHIFT)
532 #define I40E_GLGEN_MSCA_OPCODE_MASK I40E_MASK(0x3, I40E_GLGEN_MSCA_OPCODE_SHIFT)
534 #define I40E_GLGEN_MSCA_STCODE_MASK I40E_MASK(0x3, I40E_GLGEN_MSCA_STCODE_SHIFT)
552 #define I40E_GLGEN_RSTAT_DEVSTATE_MASK I40E_MASK(0x3, I40E_GLGEN_RSTAT_DEVSTATE_SHIF
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/freebsd-11-stable/sys/arm/nvidia/tegra124/
H A Dtegra124_xusbpadctl.c74 #define USB2_PORT_CAP_PORT_CAP_OTG 0x3
125 #define USB2_OTG_PAD_CTL1_RPU_RANGE_ADJ(x) (((x) & 0x3) << 11)
126 #define USB2_OTG_PAD_CTL1_HS_IREF_CAP(x) (((x) & 0x3) << 9)
127 #define USB2_OTG_PAD_CTL1_SPARE(x) (((x) & 0x3) << 7)
137 #define USB2_BIAS_PAD_CTL0_TERM_OFFSETL(x) (((x) & 0x3) << 9)
138 #define USB2_BIAS_PAD_CTL0_VBUS_LEVEL(x) (((x) & 0x3) << 7)
139 #define USB2_BIAS_PAD_CTL0_HS_CHIRP_LEVEL(x) (((x) & 0x3) << 5)
141 #define USB2_BIAS_PAD_CTL0_HS_SQUELCH_LEVEL(x) (((x) & 0x3) << 0)
322 LANE("usb2", 0, XUSB_PADCTL_USB2_PAD_MUX, 0, 0x3, otg_mux),
323 LANE("usb2", 1, XUSB_PADCTL_USB2_PAD_MUX, 2, 0x3, otg_mu
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Completed in 344 milliseconds

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