Searched refs:getOpcode (Results 201 - 225 of 780) sorted by relevance

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/freebsd-11-stable/contrib/llvm-project/llvm/lib/CodeGen/
H A DTargetInstrInfo.cpp473 switch (MI.getOpcode()) {
502 MF.CreateMachineInstr(TII.get(MI.getOpcode()), MI.getDebugLoc(), true);
572 if (MI.getOpcode() == TargetOpcode::STACKMAP ||
573 MI.getOpcode() == TargetOpcode::PATCHPOINT ||
574 MI.getOpcode() == TargetOpcode::STATEPOINT) {
637 if ((MI.getOpcode() == TargetOpcode::STACKMAP ||
638 MI.getOpcode() == TargetOpcode::PATCHPOINT ||
639 MI.getOpcode() == TargetOpcode::STATEPOINT) &&
693 unsigned AssocOpcode = Inst.getOpcode();
697 Commuted = MI1->getOpcode() !
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H A DXRayInstrumentation.cpp98 (op.HandleAllReturns || T.getOpcode() == TII->getReturnOpcode())) {
110 .addImm(T.getOpcode());
131 (op.HandleAllReturns || T.getOpcode() == TII->getReturnOpcode())) {
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/WebAssembly/
H A DWebAssemblyMCInstLower.cpp208 OutMI.setOpcode(MI->getOpcode());
249 if (WebAssembly::isCallIndirect(MI->getOpcode()))
254 if (MI->getOpcode() == WebAssembly::RET_CALL_INDIRECT)
329 auto RegOpcode = OutMI.getOpcode();
H A DWebAssemblyExplicitLocals.cpp209 if (!WebAssembly::isArgument(MI.getOpcode()))
231 assert(!WebAssembly::isArgument(MI.getOpcode()));
239 if (WebAssembly::isTee(MI.getOpcode())) {
281 if (MI.getOpcode() == WebAssembly::IMPLICIT_DEF) {
365 if (WebAssembly::isCopy(MI.getOpcode())) {
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/NVPTX/
H A DNVPTXTargetTransformInfo.h107 switch(I->getOpcode()){
H A DNVPTXISelDAGToDAG.cpp84 switch (N->getOpcode()) {
616 if (U->getOpcode() != ISD::EXTRACT_VECTOR_ELT)
640 if (Vector->getOpcode() == ISD::BITCAST) {
1049 switch (N->getOpcode()) {
1066 assert(N->getOpcode() == NVPTXISD::LoadV4 && "Unexpected load opcode.");
1073 switch (N->getOpcode()) {
1100 switch (N->getOpcode()) {
1128 switch (N->getOpcode()) {
1148 switch (N->getOpcode()) {
1176 switch (N->getOpcode()) {
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/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/AMDGPU/
H A DSIInstrInfo.cpp135 switch (MI.getOpcode()) {
268 unsigned Opc = LdSt.getOpcode();
626 if (Def->getOpcode() != AMDGPU::V_ACCVGPR_WRITE_B32)
1372 switch (MI.getOpcode()) {
1383 switch (MI.getOpcode()) {
1574 assert (MI.getOpcode() == AMDGPU::V_MOV_B64_DPP_PSEUDO);
1679 unsigned Opc = MI.getOpcode();
1737 unsigned Opc = Desc.getOpcode();
1767 if (MI.getOpcode() == AMDGPU::S_SETPC_B64) {
1916 if (I->getOpcode()
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H A DSILowerI1Copies.cpp179 if (MI.getOpcode() == AMDGPU::SI_NON_UNIFORM_BRCOND_PSEUDO ||
180 MI.getOpcode() == AMDGPU::SI_IF ||
181 MI.getOpcode() == AMDGPU::SI_ELSE ||
182 MI.getOpcode() == AMDGPU::SI_LOOP) {
507 if (MI.getOpcode() != AMDGPU::COPY)
581 if (IncomingDef->getOpcode() == AMDGPU::COPY) {
585 } else if (IncomingDef->getOpcode() == AMDGPU::IMPLICIT_DEF) {
677 if (MI.getOpcode() != AMDGPU::IMPLICIT_DEF &&
678 MI.getOpcode() != AMDGPU::COPY)
694 if (MI.getOpcode()
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H A DAMDGPUISelDAGToDAG.cpp106 assert(N->getOpcode() == ISD::BUILD_VECTOR && N->getNumOperands() == 2);
341 return Val.getOpcode() == ISD::BITCAST ? Val.getOperand(0) : Val;
347 if (In.getOpcode() != ISD::TRUNCATE)
351 if (Srl.getOpcode() == ISD::SRL) {
366 if (In.getOpcode() == ISD::TRUNCATE) {
508 switch (N->getOpcode()) {
566 if (N->getOpcode() == ISD::CopyToReg) {
615 return CurDAG->MorphNodeTo(N, N->getOpcode(), N->getVTList(), Ops);
716 assert(N->getOpcode() == ISD::SCALAR_TO_VECTOR && NOps < NumVectorElts);
733 unsigned int Opc = N->getOpcode();
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/freebsd-11-stable/contrib/llvm-project/clang/lib/ARCMigrate/
H A DTransZeroOutPropsInDealloc.cpp161 if (BOE->getOpcode() == BO_Comma)
165 if (BOE->getOpcode() != BO_Assign)
195 if (BO->getOpcode() != BO_Assign) return false;
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/Lanai/Disassembler/
H A DLanaiDisassembler.cpp94 if (isRMOpcode(Instr.getOpcode()))
96 else if (isSPLSOpcode(Instr.getOpcode()))
98 else if (isRRMOpcode(Instr.getOpcode())) {
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/Lanai/
H A DLanaiDelaySlotFiller.cpp103 if (I->getOpcode() == Lanai::RET) {
108 assert(RI->getOpcode() == Lanai::LDW_RI && RI->getOperand(0).isReg() &&
114 assert(RI->getOpcode() == Lanai::ADD_I_LO &&
H A DLanaiAsmPrinter.cpp150 assert((MI->getOpcode() == Lanai::CALL || MI->getOpcode() == Lanai::CALLR) &&
174 if (MI->getOpcode() == Lanai::CALL) {
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/Mips/
H A DMipsInstructionSelector.cpp107 LLVM_DEBUG(dbgs() << "Failed to constrain " << TII.getName(I.getOpcode())
174 /// When I.getOpcode() is returned, we failed to select MIPS instruction opcode.
182 unsigned Opc = I.getOpcode();
257 if (!isPreISelGenericOpcode(I.getOpcode())) {
264 if (I.getOpcode() == Mips::G_MUL &&
285 switch (I.getOpcode()) {
408 if (NewOpc == I.getOpcode())
421 if (Addr->getOpcode() == G_PTR_ADD) {
423 if (Offset->getOpcode() == G_CONSTANT) {
444 bool IsSigned = I.getOpcode()
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H A DMicroMipsSizeReduction.cpp355 !(MI->getOpcode() == Mips::LW || MI->getOpcode() == Mips::LW_MM ||
356 MI->getOpcode() == Mips::LW16_MM))
360 !(MI->getOpcode() == Mips::SW || MI->getOpcode() == Mips::SW_MM ||
361 MI->getOpcode() == Mips::SW16_MM))
418 unsigned Opcode = MI->getOpcode();
468 bool ReduceToLwp = (MI1->getOpcode() == Mips::LW) ||
469 (MI1->getOpcode() == Mips::LW_MM) ||
470 (MI1->getOpcode()
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/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/X86/
H A DX86EvexToVex.cpp149 unsigned Opc = MI.getOpcode();
255 auto I = llvm::lower_bound(Table, MI.getOpcode());
256 if (I == Table.end() || I->EvexOpcode != MI.getOpcode())
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/X86/MCTargetDesc/
H A DX86AsmBackend.cpp182 unsigned Op = Inst.getOpcode();
194 unsigned Op = Inst.getOpcode();
280 if (R != Inst.getOpcode())
287 unsigned Opcode = MI.getOpcode();
307 unsigned Opcode = MI.getOpcode();
326 X86::classifyFirstOpcodeInMacroFusion(Inst.getOpcode());
332 const MCInstrDesc &InstDesc = MCII->get(Jcc.getOpcode());
338 X86::classifyFirstOpcodeInMacroFusion(Cmp.getOpcode());
387 const MCInstrDesc &InstDesc = MCII->get(Inst.getOpcode());
589 if (getRelaxedOpcodeBranch(Inst, false) != Inst.getOpcode())
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/freebsd-11-stable/contrib/llvm-project/llvm/include/llvm/IR/
H A DInstrTypes.h81 I->getOpcode() == Instruction::Alloca ||
82 I->getOpcode() == Instruction::Load ||
83 I->getOpcode() == Instruction::VAArg ||
84 I->getOpcode() == Instruction::ExtractValue ||
85 (I->getOpcode() >= CastOpsBegin && I->getOpcode() < CastOpsEnd);
171 UnaryOps getOpcode() const { function in class:llvm::UnaryOperator
172 return static_cast<UnaryOps>(Instruction::getOpcode());
402 BinaryOps getOpcode() const { function in class:llvm::BinaryOperator
403 return static_cast<BinaryOps>(Instruction::getOpcode());
692 Instruction::CastOps getOpcode() const { function in class:llvm::CastInst
802 OtherOps getOpcode() const { function in class:llvm::CmpInst
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/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/ARM/
H A DMLxExpansionPass.cpp188 unsigned Opcode = MCID.getOpcode();
218 if (TII->isFpMLxInstruction(DefMI->getOpcode())) {
235 return isFpMulInstruction(DefMI->getOpcode()) || hasLoopHazard(MI);
253 if (TII->canCauseFpMLxStall(NextMI->getOpcode())) {
356 if (!TII->isFpMLxInstruction(MCID.getOpcode(),
H A DARMConstantIslandPass.cpp568 switch (MI->getOpcode()) {
654 switch (CPEMI->getOpcode()) {
681 (I.getOpcode() == ARM::t2BR_JT || I.getOpcode() == ARM::tBR_JTr))
712 unsigned Opc = I.getOpcode();
1094 if (PredMI->getOpcode() == ARM::B || PredMI->getOpcode() == ARM::tB
1095 || PredMI->getOpcode() == ARM::t2B)
1369 I->getOpcode() != ARM::t2IT &&
1405 if (MI->getOpcode()
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/freebsd-11-stable/contrib/llvm-project/llvm/lib/Transforms/Scalar/
H A DNaryReassociate.cpp218 switch (I->getOpcode()) {
287 switch (I->getOpcode()) {
483 switch (I->getOpcode()) {
499 switch (I->getOpcode()) {
513 switch (I->getOpcode()) {
H A DInferAddressSpaces.cpp225 switch (Op.getOpcode()) {
245 switch (Op.getOpcode()) {
448 if (I->getOpcode() == Instruction::AddrSpaceCast) {
469 switch (I->getOpcode()) {
509 if (CE->getOpcode() == Instruction::AddrSpaceCast) {
518 if (CE->getOpcode() == Instruction::BitCast) {
524 if (CE->getOpcode() == Instruction::Select) {
567 if (CE->getOpcode() == Instruction::GetElementPtr) {
703 if (Op.getOpcode() == Instruction::Select) {
848 if (Op->getOpcode()
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/freebsd-11-stable/contrib/llvm-project/llvm/lib/Transforms/Utils/
H A DSimplifyIndVar.cpp113 switch (UseInst->getOpcode()) {
135 if (UseInst->getOpcode() == Instruction::LShr) {
623 bool IsSRem = Bin->getOpcode() == Instruction::SRem;
624 if (IsSRem || Bin->getOpcode() == Instruction::URem) {
629 if (Bin->getOpcode() == Instruction::SDiv)
735 if (BO->getOpcode() != Instruction::Add &&
736 BO->getOpcode() != Instruction::Sub &&
737 BO->getOpcode() != Instruction::Mul)
745 willNotOverflow(SE, BO->getOpcode(), /* Signed */ false, LHS, RHS)) {
752 willNotOverflow(SE, BO->getOpcode(), /* Signe
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/freebsd-11-stable/contrib/llvm-project/clang/lib/Sema/
H A DSemaConcept.cpp41 if (BinOp->getOpcode() == BO_LAnd || BinOp->getOpcode() == BO_LOr)
103 if (BO->getOpcode() == BO_LAnd || BO->getOpcode() == BO_LOr) {
110 if (BO->getOpcode() == BO_LOr && IsLHSSatisfied)
119 if (BO->getOpcode() == BO_LAnd && !IsLHSSatisfied)
491 switch (BO->getOpcode()) {
536 << BinaryOperator::getOpcodeStr(BO->getOpcode())
729 if (BO->getOpcode() == BO_LAnd || BO->getOpcode()
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/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/PowerPC/
H A DPPCReduceCRLogicals.cpp156 unsigned OrigBROpcode = BSI.OrigBranch->getOpcode();
391 unsigned Opc = MI.getOpcode();
500 unsigned Opc = UseMI.getOpcode();
628 if (CRI.MI->getOpcode() != PPC::CROR &&
629 CRI.MI->getOpcode() != PPC::CRAND &&
630 CRI.MI->getOpcode() != PPC::CRNOR &&
631 CRI.MI->getOpcode() != PPC::CRNAND &&
632 CRI.MI->getOpcode() != PPC::CRORC &&
633 CRI.MI->getOpcode() != PPC::CRANDC) {
680 unsigned Opc = CRI.MI->getOpcode();
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