Searched refs:createReg (Results 51 - 65 of 65) sorted by relevance

123

/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/WebAssembly/
H A DWebAssemblyMCInstLower.cpp229 MCOp = MCOperand::createReg(WAReg);
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/BPF/
H A DBTFDebug.cpp1177 OutMI.addOperand(MCOperand::createReg(MI->getOperand(0).getReg()));
1195 OutMI.addOperand(MCOperand::createReg(MI->getOperand(0).getReg()));
1196 OutMI.addOperand(MCOperand::createReg(MI->getOperand(2).getReg()));
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/AMDGPU/
H A DAMDGPUMCInstLower.cpp135 MCOp = MCOperand::createReg(AMDGPU::getMCReg(MO.getReg(), ST));
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/ARC/Disassembler/
H A DARCDisassembler.cpp129 Inst.addOperand(MCOperand::createReg(Reg));
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/AVR/AsmParser/
H A DAVRAsmParser.cpp133 Inst.addOperand(MCOperand::createReg(getReg()));
159 Inst.addOperand(MCOperand::createReg(getReg()));
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/XCore/Disassembler/
H A DXCoreDisassembler.cpp206 Inst.addOperand(MCOperand::createReg(Reg));
218 Inst.addOperand(MCOperand::createReg(Reg));
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/RISCV/AsmParser/
H A DRISCVAsmParser.cpp668 static std::unique_ptr<RISCVOperand> createReg(unsigned RegNo, SMLoc S, function in struct:__anon2376::RISCVOperand
714 Inst.addOperand(MCOperand::createReg(getReg()));
1064 Operands.push_back(RISCVOperand::createReg(RegNo, S, E, isRV64()));
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/AArch64/AsmParser/
H A DAArch64AsmParser.cpp1427 Inst.addOperand(MCOperand::createReg(getReg()));
1439 Inst.addOperand(MCOperand::createReg(Reg));
1451 Inst.addOperand(MCOperand::createReg(Reg));
1466 Inst.addOperand(MCOperand::createReg(AArch64::Z0 + getReg() - Base));
1473 Inst.addOperand(MCOperand::createReg(AArch64::D0 + getReg() - AArch64::Q0));
1480 Inst.addOperand(MCOperand::createReg(getReg()));
1485 Inst.addOperand(MCOperand::createReg(getReg()));
1513 Inst.addOperand(MCOperand::createReg(FirstReg + getVectorListStart() -
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/Hexagon/MCTargetDesc/
H A DHexagonMCInstrInfo.cpp358 static MCOperand MCO = MCOperand::createReg(Hexagon::VTMP);
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/ARM/
H A DThumb2InstrInfo.cpp49 NopInst.addOperand(MCOperand::createReg(0));
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/X86/
H A DX86MCInstLower.cpp408 return MCOperand::createReg(MO.getReg());
744 OutMI.addOperand(MCOperand::createReg(ReturnReg));
1226 CallTargetMCOp = MCOperand::createReg(CallTarget.getReg());
1274 MI.addOperand(MCOperand::createReg(DefRegister));
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/ARM/MCTargetDesc/
H A DARMAsmBackend.cpp334 Res.addOperand(MCOperand::createReg(0));
H A DARMInstPrinter.cpp272 NewReg = MCOperand::createReg(MRI.getMatchingSuperReg(
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/AMDGPU/AsmParser/
H A DAMDGPUAsmParser.cpp1865 Inst.addOperand(MCOperand::createReg(AMDGPU::getMCReg(getReg(), AsmParser->getSTI())));
4789 Inst.addOperand(MCOperand::createReg(AMDGPU::M0)); // m0
4825 Inst.addOperand(MCOperand::createReg(AMDGPU::M0)); // m0
4850 Inst.addOperand(MCOperand::createReg(AMDGPU::NoRegister));
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/NVPTX/
H A DNVPTXAsmPrinter.cpp244 MCOp = MCOperand::createReg(encodeVirtualRegister(MO.getReg()));

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