Searched refs:WR4 (Results 26 - 50 of 60) sorted by relevance

123

/freebsd-11-stable/sys/arm/nvidia/
H A Dtegra_i2c.c194 #define WR4(_sc, _r, _v) bus_write_4((_sc)->mem_res, (_r), (_v)) macro
246 WR4(sc, I2C_FIFO_CONTROL, reg);
274 WR4(sc, I2C_CLK_DIVISOR,
285 WR4(sc, I2C_BUS_CLEAR_CONFIG,
290 WR4(sc, I2C_CONFIG_LOAD, I2C_CONFIG_LOAD_MSTR_CONFIG_LOAD);
300 WR4(sc, I2C_BUS_CLEAR_CONFIG,reg);
334 WR4(sc, I2C_INTERRUPT_MASK_REGISTER, 0);
335 WR4(sc, I2C_INTERRUPT_STATUS_REGISTER, 0xFFFFFFFF);
336 WR4(sc, I2C_CNFG, I2C_CNFG_NEW_MASTER_FSM | I2C_CNFG_PACKET_MODE_EN |
341 WR4(s
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H A Dtegra_usbphy.c316 #define WR4(sc, offs, val) \ macro
343 WR4(sc, CTRL_USB_HOSTPC1_DEVLC, val);
363 WR4(sc, IF_USB_SUSP_CTRL, val);
368 WR4(sc, UTMIP_TX_CFG0, val);
375 WR4(sc, UTMIP_HSRX_CFG0, val);
380 WR4(sc, UTMIP_HSRX_CFG1, val);
385 WR4(sc, UTMIP_DEBOUNCE_CFG0, val);
389 WR4(sc, UTMIP_MISC_CFG0, val);
395 WR4(sc, IF_USB_SUSP_CTRL, val);
399 WR4(s
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H A Dtegra_mc.c99 #define WR4(_sc, _r, _v) bus_write_4((_sc)->mem_res, (_r), (_v)) macro
149 WR4(sc, MC_INTSTATUS, stat);
183 WR4(sc, MC_INTSTATUS, stat);
191 WR4(sc, MC_INTMASK, 0);
192 WR4(sc, MC_INTSTATUS, MC_INT_INT_MASK);
262 WR4(sc, MC_INTMASK, MC_INT_INT_MASK);
H A Dtegra_soctherm.c126 #define WR4(_sc, _r, _v) bus_write_4((_sc)->mem_res, (_r), (_v)) macro
377 WR4(sc, sensor->sensor_base + TSENSOR_CONFIG0, val);
381 WR4(sc, sensor->sensor_base + TSENSOR_CONFIG0, val);
387 WR4(sc, sensor->sensor_base + TSENSOR_CONFIG1, val);
391 WR4(sc, sensor->sensor_base + TSENSOR_CONFIG2, val);
395 WR4(sc, sensor->sensor_base + TSENSOR_CONFIG0, val);
624 WR4(sc, TSENSOR_PDIV, TSENSOR_PDIV_T124);
625 WR4(sc, TSENSOR_HOTSPOT_OFF, TSENSOR_HOTSPOT_OFF_T124);
H A Dtegra_lic.c67 #define WR4(_sc, _b, _r, _v) bus_write_4((_sc)->mem_res[_b], (_r), (_v)) macro
231 WR4(sc, i, LIC_CPU_IER_CLR, 0xFFFFFFFF);
232 WR4(sc, i, LIC_CPU_IEP_CLASS, 0);
/freebsd-11-stable/sys/arm/freescale/imx/
H A Dimx6_snvs.c89 WR4(struct snvs_softc *sc, bus_size_t offset, uint32_t value) function
104 WR4(sc, SNVS_LPCR, sc->lpcr);
163 WR4(sc, SNVS_LPSRTCMR, (uint32_t)(sbt >> (SBT_LSB + 32)));
164 WR4(sc, SNVS_LPSRTCLR, (uint32_t)(sbt >> (SBT_LSB)));
H A Dimx_iomux.c114 WR4(struct iomux_softc *sc, bus_size_t off, uint32_t val) function
143 WR4(sc, reg, val);
165 WR4(sc, cfg->mux_reg, cfg->mux_val | sion);
168 WR4(sc, cfg->padconf_reg, cfg->padconf_val);
289 WR4(iomux_sc, regaddr, val);
306 WR4(iomux_sc, regaddr, val);
H A Dimx6_src.c66 WR4(struct src_softc *sc, bus_size_t off, uint32_t val) function
83 WR4(src_sc, SRC_SCR, reg);
H A Dimx_spi.c162 WR4(struct spi_softc *sc, bus_size_t offset, uint32_t value) function
242 WR4(sc, ECSPI_CTLREG, sc->ctlreg);
258 WR4(sc, ECSPI_CFGREG, reg);
265 WR4(sc, ECSPI_DMAREG, reg);
289 WR4(sc, ECSPI_TXDATA, sc->txbuf[sc->txidx++]);
312 WR4(sc, ECSPI_STATREG, status); /* Clear w1c bits. */
360 WR4(sc, ECSPI_INTREG, sc->intreg);
397 WR4(sc, ECSPI_INTREG, sc->intreg);
450 WR4(sc, ECSPI_CTLREG, 0);
560 WR4(s
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/freebsd-11-stable/sys/dev/cadence/
H A Dif_cgem.c195 #define WR4(sc, off, val) (bus_write_4((sc)->mem_res, (off), (val))) macro
259 WR4(sc, CGEM_SPEC_ADDR_LOW(0), (eaddr[3] << 24) |
261 WR4(sc, CGEM_SPEC_ADDR_HI(0), (eaddr[5] << 8) | eaddr[4]);
264 WR4(sc, CGEM_SPEC_ADDR_LOW(i), 0);
265 WR4(sc, CGEM_SPEC_ADDR_HI(i), 0);
350 WR4(sc, CGEM_HASH_TOP, hash_hi);
351 WR4(sc, CGEM_HASH_BOT, hash_lo);
352 WR4(sc, CGEM_NET_CFG, net_cfg);
809 WR4(sc, CGEM_NET_CTRL, sc->net_ctl_shadow |
916 WR4(s
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/freebsd-11-stable/sys/dev/sdhci/
H A Dfsl_sdhci.c193 WR4(struct fsl_sdhci_softc *sc, bus_size_t off, uint32_t val) function
396 WR4(sc, SDHC_PROT_CTRL, val32);
414 WR4(sc, off & ~3, val32);
454 WR4(sc, SDHCI_INT_ENABLE, slot->intmask | SDHCI_INT_RESPONSE);
455 WR4(sc, SDHCI_SIGNAL_ENABLE, slot->intmask | SDHCI_INT_RESPONSE);
474 WR4(sc, USDHC_MIX_CONTROL, val32);
485 WR4(sc, SDHCI_TRANSFER_MODE, sc->cmd_and_mode);
493 WR4(sc, off & ~3, val32);
506 WR4(sc, off, val);
590 WR4(s
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H A Dsdhci.c80 #define WR4(slot, off, val) SDHCI_WRITE_4((slot)->bus, (slot), (off), (val)) macro
308 WR4(slot, SDHCI_INT_ENABLE, slot->intmask);
309 WR4(slot, SDHCI_SIGNAL_ENABLE, slot->intmask);
532 WR4(slot, SDHCI_BUFFER, data);
546 WR4(slot, SDHCI_BUFFER, data);
600 WR4(slot, SDHCI_INT_ENABLE, slot->intmask);
601 WR4(slot, SDHCI_SIGNAL_ENABLE, slot->intmask);
1179 WR4(slot, SDHCI_SIGNAL_ENABLE, 0);
1327 WR4(slot, SDHCI_INT_ENABLE, slot->intmask);
1328 WR4(slo
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/freebsd-11-stable/sys/arm/allwinner/
H A Dif_awg.c72 #define WR4(sc, reg, val) bus_write_4((sc)->res[0], (reg), (val)) macro
179 WR4(sc, EMAC_MII_CMD,
207 WR4(sc, EMAC_MII_DATA, val);
208 WR4(sc, EMAC_MII_CMD,
271 WR4(sc, EMAC_BASIC_CTL_0, val);
277 WR4(sc, EMAC_RX_CTL_0, val);
285 WR4(sc, EMAC_TX_FLOW_CTL, val);
510 WR4(sc, EMAC_TX_CTL_1, val | TX_DMA_START);
613 WR4(sc, EMAC_ADDR_HIGH(0), machi);
614 WR4(s
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/freebsd-11-stable/sys/arm/at91/
H A Dat91_pmc.c184 WR4(struct at91_pmc_softc *sc, bus_size_t off, uint32_t val) function
243 WR4(sc, CKGR_PLLBR, value);
261 WR4(sc, CKGR_UCKR, RD4(sc, CKGR_UCKR) | value);
265 WR4(sc, PMC_USB, PMC_USB_USBDIV(9) | PMC_USB_USBS);
266 WR4(sc, PMC_SCER, PMC_SCER_UHP_SAM9);
274 WR4(sc, on ? PMC_SCER : PMC_SCDR, clk->pmc_mask);
288 WR4(sc, on ? PMC_PCER : PMC_PCDR, clk->pmc_mask);
578 WR4(sc, PMC_SCDR, PMC_SCER_UHP | PMC_SCER_UDP);
579 WR4(sc, PMC_SCER, PMC_SCER_MCKUDP);
581 WR4(s
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H A Dat91_wdt.c75 WR4(struct wdt_softc *sc, bus_size_t off, uint32_t val) function
133 WR4(sc, WDT_CR, WDT_KEY|WDT_WDRSTT);
178 WR4(sc, WDT_MR, WDT_WDDBGHLT | WDT_WDD(0xC00)|
182 WR4(sc, WDT_MR, WDT_WDDBGHLT | WDT_WDD(0xC00)|
H A Dat91_pit.c80 WR4(struct pit_softc *sc, bus_size_t off, uint32_t val) function
166 WR4(sc, PIT_MR, PIT_PIV(at91_master_clock / PIT_PRESCALE / hz) |
/freebsd-11-stable/sys/arm/xscale/ixp425/
H A Dif_npe.c206 WR4(struct npe_softc *sc, bus_size_t off, uint32_t val) function
457 WR4(sc, NPE_MAC_ADDR_MASK(i), mask[i]);
458 WR4(sc, NPE_MAC_ADDR(i), addr[i]);
657 WR4(sc, NPE_MAC_CORE_CNTRL, NPE_CORE_RESET);
660 WR4(sc, NPE_MAC_CORE_CNTRL, NPE_CORE_MDC_EN);
962 WR4(sc, NPE_MAC_UNI_ADDR_1, eaddr[0]);
963 WR4(sc, NPE_MAC_UNI_ADDR_2, eaddr[1]);
964 WR4(sc, NPE_MAC_UNI_ADDR_3, eaddr[2]);
965 WR4(sc, NPE_MAC_UNI_ADDR_4, eaddr[3]);
966 WR4(s
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/freebsd-11-stable/sys/arm/nvidia/tegra124/
H A Dtegra124_pmc.c136 #define WR4(_sc, _r, _v) bus_write_4((_sc)->mem_res, (_r), (_v)) macro
208 WR4(sc, PMC_PWRGATE_TOGGLE,
235 WR4(sc, PMC_GPU_RG_CNTRL, 0);
249 WR4(sc, PMC_REMOVE_CLAMPING_CMD, PMC_REMOVE_CLAMPING_CMD_PARTID(swid));
516 WR4(sc, PMC_CNTRL, reg);
524 WR4(sc, PMC_CNTRL, reg);
529 WR4(sc, PMC_CNTRL, reg);
537 WR4(sc, PMC_IO_DPD_STATUS, reg);
541 WR4(sc, PMC_IO_DPD2_STATUS, reg);
H A Dtegra124_clk_super.c214 WR4(sc, sc->base_reg, reg);
218 WR4(sc, sc->base_reg, reg);
225 WR4(sc, sc->base_reg, reg);
/freebsd-11-stable/sys/dev/tpm/
H A Dtpm20.h168 WR4(struct tpm_sc *sc, bus_size_t off, uint32_t val) function
177 WR4(sc, off, RD4(sc, off) & val);
189 WR4(sc, off, RD4(sc, off) | val);
H A Dtpm_crb.c295 WR4(sc, TPM_CRB_CTRL_CANCEL, TPM_CRB_CTRL_CANCEL_CMD);
303 WR4(sc, TPM_CRB_CTRL_CANCEL, TPM_CRB_CTRL_CANCEL_CLEAR);
335 WR4(sc, TPM_CRB_CTRL_CANCEL, TPM_CRB_CTRL_CANCEL_CLEAR);
373 WR4(sc, TPM_CRB_CTRL_START, TPM_CRB_CTRL_START_CMD);
/freebsd-11-stable/sys/mips/mediatek/
H A Dmtk_xhci.c252 #define WR4(_sc, _reg, _val) bus_write_4((_sc)->sc_io_res, (_reg), (_val)) macro
254 WR4((_sc), (_reg), (RD4((_sc), (_reg)) & ~(_clr)) | (_set))
283 WR4(sc, USB_HDMA_CFG, USB_HDMA_CFG_MT7621_VAL);
284 WR4(sc, U3_LTSSM_TIMING_PARAM3, U3_LTSSM_TIMING_VAL);
285 WR4(sc, SYNC_HS_EOF, SYNC_HS_EOF_VAL);
286 WR4(sc, USB_IP_SPAR0, USB_IP_SPAR0_VAL);
/freebsd-11-stable/sys/dev/mwl/
H A Dmwlhal.c221 WR4(struct mwl_hal_priv *mh, bus_size_t off, uint32_t val) function
491 WR4(mh, MACREG_REG_A2H_INTERRUPT_CAUSE,
507 WR4(mh, MACREG_REG_A2H_INTERRUPT_MASK, 0);
511 WR4(mh, MACREG_REG_A2H_INTERRUPT_MASK, mask);
528 WR4(mh, MACREG_REG_H2A_INTERRUPT_EVENTS, MACREG_H2ARIC_BIT_PPA_READY);
2174 WR4(mh, MACREG_REG_PROMISCUOUS, ena ? v | 1 : v &~ 1);
2351 WR4(mh, MACREG_REG_GEN_PTR, mh->mh_cmdaddr);
2354 WR4(mh, MACREG_REG_H2A_INTERRUPT_EVENTS, MACREG_H2ARIC_BIT_DOOR_BELL);
2440 WR4(mh, MACREG_REG_H2A_INTERRUPT_EVENTS, ISR_RESET);
2451 WR4(m
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/freebsd-11-stable/sys/arm/ti/
H A Dti_sdhci.c147 WR4(struct ti_sdhci_softc *sc, bus_size_t off, uint32_t val) function
248 WR4(sc, off & ~3, val32);
276 WR4(sc, SDHCI_CLOCK_CONTROL, val32);
290 WR4(sc, SDHCI_TRANSFER_MODE, sc->cmd_and_mode);
297 WR4(sc, off & ~3, val32);
306 WR4(sc, off, val);
/freebsd-11-stable/sys/dev/extres/clk/
H A Dclk_mux.c43 #define WR4(_clk, off, val) \ macro

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