Searched refs:V0 (Results 26 - 50 of 59) sorted by relevance

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/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/SystemZ/MCTargetDesc/
H A DSystemZMCTargetDesc.cpp103 SystemZ::V0, SystemZ::V1, SystemZ::V2, SystemZ::V3,
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Transforms/Scalar/
H A DReassociate.cpp126 Value *V0 = I->getOperand(0); local
129 if (match(V0, m_APInt(C)))
130 std::swap(V0, V1);
134 SymbolicPart = V0;
934 Value *V0 = Sub->getOperand(0);
935 if (isReassociableOp(V0, Instruction::Add, Instruction::FAdd) ||
936 isReassociableOp(V0, Instruction::Sub, Instruction::FSub))
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Transforms/InstCombine/
H A DInstCombineAddSub.cpp390 Value *V0 = I->getOperand(0); local
392 if (ConstantFP *C = dyn_cast<ConstantFP>(V0)) {
398 Addend0.set(C, V0);
468 Value *V0 = I->getOperand(0); local
470 InstQuota = ((!isa<Constant>(V0) && V0->hasOneUse()) &&
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Analysis/
H A DVectorUtils.cpp735 Value *V0 = ResList[i], *V1 = ResList[i + 1]; local
736 assert((V0->getType() == V1->getType() || i == NumVecs - 2) &&
739 TmpList.push_back(concatenateTwoVectors(Builder, V0, V1));
H A DBasicAliasAnalysis.cpp2006 const Value *V0 = GetLinearExpression(Var0.V, V0Scale, V0Offset, V0ZExtBits, local
2014 V0SExtBits != V1SExtBits || !isValueEqualInPotentialCycles(V0, V1))
/freebsd-11-stable/contrib/groff/src/roff/troff/
H A Dnumber.cpp31 vunits V0; variable
/freebsd-11-stable/sys/mips/mips/
H A Dpm_machdep.c339 mcp->mc_regs[V0] = 0;
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/Hexagon/
H A DHexagonRegisterInfo.cpp69 V0, V1, V2, V3, V4, V5, V6, V7, V8, V9, V10, V11, V12, V13,
H A DHexagonLoopIdiomRecognition.cpp1754 uint32_t V0 = C0->getZExtValue();
1756 if (V0 != (V0 & V1))
H A DHexagonCopyToCombine.cpp233 return (Reg - Hexagon::V0) % 2 == 0;
H A DHexagonInstrInfo.cpp1154 .addReg(Hexagon::V0, RegState::Undef)
1155 .addReg(Hexagon::V0, RegState::Undef);
1161 .addReg(Hexagon::V0, RegState::Undef)
1162 .addReg(Hexagon::V0, RegState::Undef);
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/Hexagon/MCTargetDesc/
H A DHexagonMCInstrInfo.cpp878 if (Consumer >= Hexagon::V0 && Consumer <= Hexagon::V31)
879 return (Consumer - Hexagon::V0) & 0x1;
H A DHexagonMCCodeEmitter.cpp400 if (Consumer >= Hexagon::V0 && Consumer <= Hexagon::V31)
401 return ((Consumer - Hexagon::V0) >> 1) == (Producer - Hexagon::W0);
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/Mips/
H A DMicroMipsSizeReduction.cpp380 Mips::AT, Mips::V0, Mips::V1, Mips::A0, Mips::A1, Mips::A2, Mips::A3,
575 if (Reg == Mips::ZERO || Reg == Mips::V0 || Reg == Mips::V1 ||
H A DMips16InstrInfo.cpp235 adjustStackPtrBig(SP, -Remainder, MBB, I, Mips::V0, Mips::V1);
H A DMips16ISelLowering.cpp487 unsigned V0Reg = Mips::V0;
H A DMipsISelLowering.cpp2547 // Store stack offset in V1, store jump target in V0. Glue CopyToReg and
2550 unsigned AddrReg = ABI.IsN64() ? Mips::V0_64 : Mips::V0;
3857 unsigned V0 = ABI.IsN64() ? Mips::V0_64 : Mips::V0; local
3859 Chain = DAG.getCopyToReg(Chain, DL, V0, Val, Flag);
3861 RetOps.push_back(DAG.getRegister(V0, getPointerTy(DAG.getDataLayout())));
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/Hexagon/Disassembler/
H A DHexagonDisassembler.cpp499 Producer = ((Producer - Hexagon::W0) << 1) + SubregBit + Hexagon::V0;
570 Hexagon::V0, Hexagon::V1, Hexagon::V2, Hexagon::V3, Hexagon::V4,
/freebsd-11-stable/contrib/llvm-project/llvm/lib/CodeGen/SelectionDAG/
H A DLegalizeIntegerTypes.cpp4245 SDValue V0 = GetPromotedInteger(N->getOperand(0)); local
4247 EVT OutVT = V0.getValueType();
4249 return DAG.getVectorShuffle(OutVT, dl, V0, V1, NewMask);
4393 SDValue V0 = GetPromotedInteger(N->getOperand(0)); local
4398 V0, ConvElem, N->getOperand(2));
4411 SDValue V0 = GetPromotedInteger(N->getOperand(0)); local
4415 V0->getValueType(0).getScalarType(), V0, V1);
4425 SDValue V0 = GetPromotedInteger(N->getOperand(0)); local
4426 MVT InVT = V0
[all...]
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/X86/
H A DX86ISelLowering.cpp8865 SDValue &V0, SDValue &V1) {
8876 V0 = DAG.getUNDEF(VT);
8914 if (V0.isUndef()) {
8915 V0 = Op0.getOperand(0);
8916 if (V0.getValueType() != VT)
8929 SDValue Expected = (i * 2 < NumElts) ? V0 : V1;
8949 /// This function expects two 256-bit vectors called V0 and V1.
8956 /// \p Mode specifies how the 128-bit parts of V0 and V1 are passed in input to
8959 /// the lower 128-bit of V0 and the upper 128-bit of V0
[all...]
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/Mips/MCTargetDesc/
H A DMipsMCCodeEmitter.cpp1126 case Mips::V0: return 2;
/freebsd-11-stable/contrib/llvm-project/llvm/lib/IR/
H A DAutoUpgrade.cpp2542 Value *V0 = (Imm & 0x02) ? CI->getArgOperand(1) : CI->getArgOperand(0); local
2546 V0 = (Imm & 0x08) ? ConstantAggregateZero::get(CI->getType()) : V0;
2559 Rep = Builder.CreateShuffleVector(V0, V1, ShuffleMask);
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Transforms/Utils/
H A DSimplifyCFG.cpp2359 auto CanHoistNotFromBothValues = [](Value *V0, Value *V1) {
2360 if (!match(V0, m_Not(m_Value())))
2361 std::swap(V0, V1);
2363 return match(V0, m_Not(m_Value())) && match(V1, Invertible);
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Transforms/Vectorize/
H A DSLPVectorizer.cpp4527 Value *V0, *V1;
4529 V0 = Builder.CreateBinOp(
4534 V0 = Builder.CreateCast(
4559 propagateIRFlags(V0, OpScalars);
4562 Value *V = Builder.CreateShuffleVector(V0, V1, ShuffleMask);
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/PowerPC/
H A DPPCAsmPrinter.cpp274 Reg = PPC::VSX32 + (Reg - PPC::V0);

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