Searched refs:Subtarget (Results 26 - 50 of 170) sorted by relevance

1234567

/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/X86/
H A DX86LegalizerInfo.h29 const X86Subtarget &Subtarget; member in class:llvm::X86LegalizerInfo
H A DX86ISelLowering.cpp111 : TargetLowering(TM), Subtarget(STI) {
112 bool UseX87 = !Subtarget.useSoftFloat() && Subtarget.hasX87();
113 X86ScalarSSEf64 = Subtarget.hasSSE2();
114 X86ScalarSSEf32 = Subtarget.hasSSE1();
127 if (Subtarget.isAtom())
129 else if (Subtarget.is64Bit())
133 const X86RegisterInfo *RegInfo = Subtarget.getRegisterInfo();
138 if (Subtarget.hasSlowDivide32())
140 if (Subtarget
2612 Passv64i1ArgInRegs( const SDLoc &Dl, SelectionDAG &DAG, SDValue &Arg, SmallVectorImpl<std::pair<unsigned, SDValue>> &RegsToPass, CCValAssign &VA, CCValAssign &NextVA, const X86Subtarget &Subtarget) argument
2904 getv64i1Argument(CCValAssign &VA, CCValAssign &NextVA, SDValue &Root, SelectionDAG &DAG, const SDLoc &Dl, const X86Subtarget &Subtarget, SDValue *InFlag = nullptr) argument
3295 get64BitArgumentGPRs(CallingConv::ID CallConv, const X86Subtarget &Subtarget) argument
3313 get64BitArgumentXMMs(MachineFunction &MF, CallingConv::ID CallConv, const X86Subtarget &Subtarget) argument
[all...]
H A DX86LegalizerInfo.cpp60 : Subtarget(STI), TM(TM) {
146 if (!Subtarget.is64Bit()) {
201 if (!Subtarget.is64Bit())
285 if (!Subtarget.hasSSE1())
314 if (!Subtarget.hasSSE2())
361 if (!Subtarget.hasSSE41())
370 if (!Subtarget.hasAVX())
413 if (!Subtarget.hasAVX2())
445 if (!Subtarget.hasAVX512())
483 if (!Subtarget
[all...]
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/Hexagon/
H A DHexagonAsmPrinter.h30 const HexagonSubtarget *Subtarget = nullptr; member in class:llvm::HexagonAsmPrinter
38 Subtarget = &Fn.getSubtarget<HexagonSubtarget>();
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/PowerPC/
H A DPPCFrameLowering.cpp101 Subtarget(STI), ReturnSaveOffset(computeReturnSaveOffset(Subtarget)),
102 TOCSaveOffset(computeTOCSaveOffset(Subtarget)),
103 FramePointerSaveOffset(computeFramePointerSaveOffset(Subtarget)),
104 LinkageSize(computeLinkageSize(Subtarget)),
105 BasePointerSaveOffset(computeBasePointerSaveOffset(Subtarget)),
111 if (Subtarget.isDarwinABI()) {
113 if (Subtarget.isPPC64()) {
123 if (!Subtarget.isSVR4ABI()) {
273 if (Subtarget
[all...]
H A DPPCISelLowering.cpp139 : TargetLowering(TM), Subtarget(STI) {
142 bool isPPC64 = Subtarget.isPPC64();
170 if (Subtarget.isISA3_0()) {
200 if (!Subtarget.hasSPE()) {
216 if (Subtarget.useCRBits()) {
219 if (isPPC64 || Subtarget.hasFPCVT()) {
267 if (Subtarget.isISA3_0()) {
300 if (Subtarget.hasSPE()) {
311 if (!Subtarget.hasFSQRT() &&
312 !(TM.Options.UnsafeFPMath && Subtarget
1598 const PPCSubtarget& Subtarget = local
2697 getLabelAccessInfo(bool IsPIC, const PPCSubtarget &Subtarget, unsigned &HiOpFlags, unsigned &LoOpFlags, const GlobalValue *GV = nullptr) argument
4612 needStackSlotPassParameters(const PPCSubtarget &Subtarget, const SmallVectorImpl<ISD::OutputArg> &Outs) argument
4868 const PPCSubtarget &Subtarget = MF.getSubtarget<PPCSubtarget>(); local
5079 isIndirectCall(const SDValue &Callee, SelectionDAG &DAG, const PPCSubtarget &Subtarget, bool isPatchPoint) argument
5100 getCallOpcode(bool isIndirectCall, bool isPatchPoint, bool isTailCall, const Function &Caller, const SDValue &Callee, const PPCSubtarget &Subtarget, const TargetMachine &TM) argument
5147 transformCallee(const SDValue &Callee, SelectionDAG &DAG, const SDLoc &dl, const PPCSubtarget &Subtarget) argument
5270 prepareDescriptorIndirectCall(SelectionDAG &DAG, SDValue &Callee, SDValue &Glue, SDValue &Chain, SDValue CallSeqStart, ImmutableCallSite CS, const SDLoc &dl, bool hasNest, const PPCSubtarget &Subtarget) argument
5363 buildCallOperands(SmallVectorImpl<SDValue> &Ops, CallingConv::ID CallConv, const SDLoc &dl, bool isTailCall, bool isVarArg, bool isPatchPoint, bool hasNest, SelectionDAG &DAG, SmallVector<std::pair<unsigned, SDValue>, 8> &RegsToPass, SDValue Glue, SDValue Chain, SDValue &Callee, int SPDiff, const PPCSubtarget &Subtarget, bool isIndirect) argument
6895 const PPCSubtarget &Subtarget = static_cast<const PPCSubtarget &>( local
7021 const PPCSubtarget &Subtarget = local
7095 const PPCSubtarget& Subtarget = local
11978 getEstimateRefinementSteps(EVT VT, const PPCSubtarget &Subtarget) argument
15542 combineADDToADDZE(SDNode *N, SelectionDAG &DAG, const PPCSubtarget &Subtarget) argument
[all...]
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/Mips/
H A DMipsAsmPrinter.cpp79 Subtarget = &MF.getSubtarget<MipsSubtarget>();
82 if (Subtarget->inMips16Mode())
96 if (Subtarget->isTargetNaCl())
118 bool InMicroMipsMode = Subtarget->inMicroMipsMode();
121 if (Subtarget->hasMips64r6()) {
125 } else if (Subtarget->hasMips32r6()) {
133 } else if (Subtarget->inMicroMipsMode())
144 unsigned ZeroReg = Subtarget->isGP64bit() ? Mips::ZERO_64 : Mips::ZERO;
165 const MipsSubtarget &Subtarget) {
179 Subtarget
161 emitDirectiveRelocJalr(const MachineInstr &MI, MCContext &OutContext, TargetMachine &TM, MCStreamer &OutStreamer, const MipsSubtarget &Subtarget) argument
[all...]
H A DMipsSEISelLowering.cpp70 if (Subtarget.isGP64bit())
73 if (Subtarget.hasDSP() || Subtarget.hasMSA()) {
85 if (Subtarget.hasDSP()) {
108 if (Subtarget.hasMips32r2()) {
114 if (Subtarget.hasDSPR2())
117 if (Subtarget.hasMSA()) {
171 if (!Subtarget.useSoftFloat()) {
175 if (!Subtarget.isSingleFloat()) {
176 if (Subtarget
482 performANDCombine(SDNode *N, SelectionDAG &DAG, TargetLowering::DAGCombinerInfo &DCI, const MipsSubtarget &Subtarget) argument
597 performORCombine(SDNode *N, SelectionDAG &DAG, TargetLowering::DAGCombinerInfo &DCI, const MipsSubtarget &Subtarget) argument
717 shouldTransformMulToShiftsAddsSubs(APInt C, EVT VT, SelectionDAG &DAG, const MipsSubtarget &Subtarget) argument
829 performMULCombine(SDNode *N, SelectionDAG &DAG, const TargetLowering::DAGCombinerInfo &DCI, const MipsSETargetLowering *TL, const MipsSubtarget &Subtarget) argument
845 performDSPShiftCombine(unsigned Opc, SDNode *N, EVT Ty, SelectionDAG &DAG, const MipsSubtarget &Subtarget) argument
870 performSHLCombine(SDNode *N, SelectionDAG &DAG, TargetLowering::DAGCombinerInfo &DCI, const MipsSubtarget &Subtarget) argument
893 performSRACombine(SDNode *N, SelectionDAG &DAG, TargetLowering::DAGCombinerInfo &DCI, const MipsSubtarget &Subtarget) argument
939 performSRLCombine(SDNode *N, SelectionDAG &DAG, TargetLowering::DAGCombinerInfo &DCI, const MipsSubtarget &Subtarget) argument
998 performXORCombine(SDNode *N, SelectionDAG &DAG, const MipsSubtarget &Subtarget) argument
2294 lowerMSALoadIntr(SDValue Op, SelectionDAG &DAG, unsigned Intr, const MipsSubtarget &Subtarget) argument
2368 lowerMSAStoreIntr(SDValue Op, SelectionDAG &DAG, unsigned Intr, const MipsSubtarget &Subtarget) argument
[all...]
H A DMipsISelLowering.cpp117 return Subtarget.isABI_O32() || VT.getSizeInBits() == 32 ? MVT::i32
126 (Subtarget.isABI_O32() ? 32 : 64)),
301 : TargetLowering(TM), Subtarget(STI), ABI(TM.getABI()) {
308 if (Subtarget.hasMips32r6())
361 if (!(TM.Options.NoNaNsFPMath || Subtarget.inAbs2008Mode())) {
366 if (Subtarget.isGP64bit()) {
381 if (!Subtarget.isGP64bit()) {
388 if (Subtarget.isGP64bit())
414 if (Subtarget.hasCnMips()) {
428 if (!Subtarget
566 performDivRemCombine(SDNode *N, SelectionDAG &DAG, TargetLowering::DAGCombinerInfo &DCI, const MipsSubtarget &Subtarget) argument
675 performSELECTCombine(SDNode *N, SelectionDAG &DAG, TargetLowering::DAGCombinerInfo &DCI, const MipsSubtarget &Subtarget) argument
756 performCMovFPCombine(SDNode *N, SelectionDAG &DAG, TargetLowering::DAGCombinerInfo &DCI, const MipsSubtarget &Subtarget) argument
783 performANDCombine(SDNode *N, SelectionDAG &DAG, TargetLowering::DAGCombinerInfo &DCI, const MipsSubtarget &Subtarget) argument
865 performORCombine(SDNode *N, SelectionDAG &DAG, TargetLowering::DAGCombinerInfo &DCI, const MipsSubtarget &Subtarget) argument
963 performMADD_MSUBCombine(SDNode *ROOTNode, SelectionDAG &CurDAG, const MipsSubtarget &Subtarget) argument
1056 performSUBCombine(SDNode *N, SelectionDAG &DAG, TargetLowering::DAGCombinerInfo &DCI, const MipsSubtarget &Subtarget) argument
1071 performADDCombine(SDNode *N, SelectionDAG &DAG, TargetLowering::DAGCombinerInfo &DCI, const MipsSubtarget &Subtarget) argument
1103 performSHLCombine(SDNode *N, SelectionDAG &DAG, TargetLowering::DAGCombinerInfo &DCI, const MipsSubtarget &Subtarget) argument
2857 const MipsSubtarget &Subtarget = static_cast<const MipsSubtarget &>( local
[all...]
H A DMipsAsmPrinter.h117 const MipsSubtarget *Subtarget; member in class:llvm::MipsAsmPrinter
131 (Subtarget->inMips16Mode() && Subtarget->useConstantIslands());
/freebsd-11-stable/contrib/llvm-project/llvm/include/llvm/MCA/Stages/
H A DDispatchStage.h69 DispatchStage(const MCSubtargetInfo &Subtarget, const MCRegisterInfo &MRI,
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/Sparc/
H A DLeonPasses.h26 const SparcSubtarget *Subtarget = nullptr; member in class:llvm::LEONMachineFunctionPass
H A DSparcTargetMachine.h24 SparcSubtarget Subtarget; member in class:llvm::SparcTargetMachine
34 const SparcSubtarget *getSubtargetImpl() const { return &Subtarget; }
H A DDelaySlotFiller.cpp40 const SparcSubtarget *Subtarget = nullptr; member in struct:__anon2394::Filler
50 Subtarget = &F.getSubtarget<SparcSubtarget>();
108 Subtarget = &MBB.getParent()->getSubtarget<SparcSubtarget>();
109 const TargetInstrInfo *TII = Subtarget->getInstrInfo();
125 if (!Subtarget->isV9() &&
188 slot->setDesc(Subtarget->getInstrInfo()->get(SP::RET));
273 if (Subtarget->insertNOPLoad()
279 if (Subtarget->fixAllFDIVSQRT()
346 for (MCRegAliasIterator AI(Reg, Subtarget->getRegisterInfo(), true);
499 const TargetInstrInfo *TII = Subtarget
[all...]
H A DSparcFrameLowering.cpp91 const SparcSubtarget &Subtarget = MF.getSubtarget<SparcSubtarget>(); local
93 *static_cast<const SparcInstrInfo *>(Subtarget.getInstrInfo());
95 *static_cast<const SparcRegisterInfo *>(Subtarget.getRegisterInfo());
145 NumBytes = Subtarget.getAdjustedFrameSize(NumBytes);
180 int64_t Bias = Subtarget.getStackPointerBias();
264 const SparcSubtarget &Subtarget = MF.getSubtarget<SparcSubtarget>(); local
266 const SparcRegisterInfo *RegInfo = Subtarget.getRegisterInfo();
295 Subtarget.getStackPointerBias();
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/RISCV/
H A DRISCVISelDAGToDAG.cpp30 const RISCVSubtarget *Subtarget = nullptr; member in class:__anon2383::final
41 Subtarget = &MF.getSubtarget<RISCVSubtarget>();
109 MVT XLenVT = Subtarget->getXLenVT();
137 if (!Subtarget->is64Bit())
161 assert(!Subtarget->is64Bit() && "READ_CYCLE_WIDE is only used on riscv32");
193 Base = CurDAG->getTargetFrameIndex(FIN->getIndex(), Subtarget->getXLenVT());
H A DRISCVISelLowering.cpp46 : TargetLowering(TM), Subtarget(STI) {
48 if (Subtarget.isRV32E())
51 RISCVABI::ABI ABI = Subtarget.getTargetABI();
55 !Subtarget.hasStdExtF()) {
59 ABI = Subtarget.is64Bit() ? RISCVABI::ABI_LP64 : RISCVABI::ABI_ILP32;
61 !Subtarget.hasStdExtD()) {
65 ABI = Subtarget.is64Bit() ? RISCVABI::ABI_LP64 : RISCVABI::ABI_ILP32;
80 MVT XLenVT = Subtarget.getXLenVT();
85 if (Subtarget.hasStdExtF())
87 if (Subtarget
[all...]
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/WebAssembly/
H A DWebAssemblyISelDAGToDAG.cpp37 const WebAssemblySubtarget *Subtarget; member in class:__anon2439::final
42 : SelectionDAGISel(TM, OptLevel), Subtarget(nullptr) {
54 Subtarget = &MF.getSubtarget<WebAssemblySubtarget>();
57 if (Subtarget->hasAddr64())
141 !Subtarget->getTargetTriple().isOSEmscripten()) {
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/ARM/
H A DARMISelLowering.cpp424 : TargetLowering(TM), Subtarget(&STI) {
425 RegInfo = Subtarget->getRegisterInfo();
426 Itins = Subtarget->getInstrItineraryData();
431 if (!Subtarget->isTargetDarwin() && !Subtarget->isTargetIOS() &&
432 !Subtarget->isTargetWatchOS()) {
440 if (Subtarget->isTargetMachO()) {
442 if (Subtarget->isThumb() && Subtarget->hasVFP2Base() &&
443 Subtarget
3789 LowerATOMIC_FENCE(SDValue Op, SelectionDAG &DAG, const ARMSubtarget *Subtarget) argument
3826 LowerPREFETCH(SDValue Op, SelectionDAG &DAG, const ARMSubtarget *Subtarget) argument
4550 LowerSADDSUBSAT(SDValue Op, SelectionDAG &DAG, const ARMSubtarget *Subtarget) argument
5095 canChangeToInt(SDValue Op, bool &SeenZero, const ARMSubtarget *Subtarget) argument
5713 ExpandBITCAST(SDNode *N, SelectionDAG &DAG, const ARMSubtarget *Subtarget) argument
9176 ReplaceREADCYCLECOUNTER(SDNode *N, SmallVectorImpl<SDValue> &Results, SelectionDAG &DAG, const ARMSubtarget *Subtarget) argument
10836 attachMEMCPYScratchRegs(const ARMSubtarget *Subtarget, MachineInstr &MI, const SDNode *Node) argument
11105 AddCombineToVPADD(SDNode *N, SDValue N0, SDValue N1, TargetLowering::DAGCombinerInfo &DCI, const ARMSubtarget *Subtarget) argument
11133 AddCombineVUZPToVPADDL(SDNode *N, SDValue N0, SDValue N1, TargetLowering::DAGCombinerInfo &DCI, const ARMSubtarget *Subtarget) argument
11186 AddCombineBUILD_VECTORToVPADDL(SDNode *N, SDValue N0, SDValue N1, TargetLowering::DAGCombinerInfo &DCI, const ARMSubtarget *Subtarget) argument
11290 AddCombineTo64BitSMLAL16(SDNode *AddcNode, SDNode *AddeNode, TargetLowering::DAGCombinerInfo &DCI, const ARMSubtarget *Subtarget) argument
11367 AddCombineTo64bitMLAL(SDNode *AddeSubeNode, TargetLowering::DAGCombinerInfo &DCI, const ARMSubtarget *Subtarget) argument
11533 AddCombineTo64bitUMAAL(SDNode *AddeNode, TargetLowering::DAGCombinerInfo &DCI, const ARMSubtarget *Subtarget) argument
11588 PerformUMLALCombine(SDNode *N, SelectionDAG &DAG, const ARMSubtarget *Subtarget) argument
11610 PerformAddcSubcCombine(SDNode *N, TargetLowering::DAGCombinerInfo &DCI, const ARMSubtarget *Subtarget) argument
11643 PerformAddeSubeCombine(SDNode *N, TargetLowering::DAGCombinerInfo &DCI, const ARMSubtarget *Subtarget) argument
11671 PerformABSCombine(SDNode *N, TargetLowering::DAGCombinerInfo &DCI, const ARMSubtarget *Subtarget) argument
11690 PerformADDECombine(SDNode *N, TargetLowering::DAGCombinerInfo &DCI, const ARMSubtarget *Subtarget) argument
11707 PerformADDCombineWithOperands(SDNode *N, SDValue N0, SDValue N1, TargetLowering::DAGCombinerInfo &DCI, const ARMSubtarget *Subtarget) argument
11889 PerformADDCombine(SDNode *N, TargetLowering::DAGCombinerInfo &DCI, const ARMSubtarget *Subtarget) argument
11909 PerformSUBCombine(SDNode *N, TargetLowering::DAGCombinerInfo &DCI, const ARMSubtarget *Subtarget) argument
11959 PerformVMULCombine(SDNode *N, TargetLowering::DAGCombinerInfo &DCI, const ARMSubtarget *Subtarget) argument
11990 PerformMULCombine(SDNode *N, TargetLowering::DAGCombinerInfo &DCI, const ARMSubtarget *Subtarget) argument
12073 CombineANDShift(SDNode *N, TargetLowering::DAGCombinerInfo &DCI, const ARMSubtarget *Subtarget) argument
12177 PerformANDCombine(SDNode *N, TargetLowering::DAGCombinerInfo &DCI, const ARMSubtarget *Subtarget) argument
12226 PerformORCombineToSMULWBT(SDNode *OR, TargetLowering::DAGCombinerInfo &DCI, const ARMSubtarget *Subtarget) argument
12286 PerformORCombineToBFI(SDNode *N, TargetLowering::DAGCombinerInfo &DCI, const ARMSubtarget *Subtarget) argument
12429 PerformORCombine_i1(SDNode *N, TargetLowering::DAGCombinerInfo &DCI, const ARMSubtarget *Subtarget) argument
12484 PerformORCombine(SDNode *N, TargetLowering::DAGCombinerInfo &DCI, const ARMSubtarget *Subtarget) argument
12584 PerformXORCombine(SDNode *N, TargetLowering::DAGCombinerInfo &DCI, const ARMSubtarget *Subtarget) argument
12740 PerformVMOVRRDCombine(SDNode *N, TargetLowering::DAGCombinerInfo &DCI, const ARMSubtarget *Subtarget) argument
12816 PerformBUILD_VECTORCombine(SDNode *N, TargetLowering::DAGCombinerInfo &DCI, const ARMSubtarget *Subtarget) argument
12957 PerformVCMPCombine(SDNode *N, TargetLowering::DAGCombinerInfo &DCI, const ARMSubtarget *Subtarget) argument
13411 PerformVDUPCombine(SDNode *N, TargetLowering::DAGCombinerInfo &DCI, const ARMSubtarget *Subtarget) argument
13592 PerformSTORECombine(SDNode *N, TargetLowering::DAGCombinerInfo &DCI, const ARMSubtarget *Subtarget) argument
13675 PerformVCVTCombine(SDNode *N, SelectionDAG &DAG, const ARMSubtarget *Subtarget) argument
13732 PerformVDIVCombine(SDNode *N, SelectionDAG &DAG, const ARMSubtarget *Subtarget) argument
15129 isLegalT2AddressImmediate(int64_t V, EVT VT, const ARMSubtarget *Subtarget) argument
15183 isLegalAddressImmediate(int64_t V, EVT VT, const ARMSubtarget *Subtarget) argument
16209 getDivRemArgList( const SDNode *N, LLVMContext *Context, const ARMSubtarget *Subtarget) argument
[all...]
H A DARMBaseInstrInfo.cpp111 Subtarget(STI) {
136 if (Subtarget.isThumb2() || Subtarget.hasVFP2Base())
771 const ARMSubtarget &Subtarget) const {
772 unsigned Opc = Subtarget.isThumb()
773 ? (Subtarget.isMClass() ? ARM::t2MRS_M : ARM::t2MRS_AR)
781 if (Subtarget.isMClass())
791 const ARMSubtarget &Subtarget) const {
792 unsigned Opc = Subtarget.isThumb()
793 ? (Subtarget
4070 adjustDefLatency(const ARMSubtarget &Subtarget, const MachineInstr &DefMI, const MCInstrDesc &DefMCID, unsigned DefAlign) argument
[all...]
H A DARMInstrInfo.cpp94 const ARMSubtarget &Subtarget = MF.getSubtarget<ARMSubtarget>(); local
97 if (!Subtarget.useMovt()) {
113 if (!Subtarget.isGVIndirectSymbol(GV)) {
H A DARMSelectionDAGInfo.cpp26 const ARMSubtarget &Subtarget = local
28 const ARMTargetLowering *TLI = Subtarget.getTargetLowering();
131 const ARMSubtarget &Subtarget = local
144 if (!AlwaysInline && SizeVal > Subtarget.getMaxInlineSizeThreshold())
155 const unsigned MaxLoadsInLDM = Subtarget.isThumb1Only() ? 4 : 6;
173 if (NumMEMCPYs > 1 && Subtarget.hasMinSize()) {
/freebsd-11-stable/contrib/llvm-project/llvm/lib/MCA/Stages/
H A DDispatchStage.cpp28 DispatchStage::DispatchStage(const MCSubtargetInfo &Subtarget, argument
33 CarryOver(0U), CarriedOver(), STI(Subtarget), RCU(R), PRF(F) {
35 DispatchWidth = Subtarget.getSchedModel().IssueWidth;
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/ARC/
H A DARCISelLowering.h63 const ARCSubtarget &Subtarget);
78 const ARCSubtarget &Subtarget; member in class:llvm::ARCTargetLowering
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/VE/
H A DVEISelLowering.cpp101 : TargetLowering(TM), Subtarget(&STI) {
121 computeRegisterProperties(Subtarget->getRegisterInfo());

Completed in 491 milliseconds

1234567